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| author | Cathy Zhang | 2020-12-16 23:40:02 +0100 |
|---|---|---|
| committer | Eduardo Habkost | 2020-12-16 21:50:33 +0100 |
| commit | 40399ecb6959ae696c235097c773d776392fde1f (patch) | |
| tree | d10fa5dea0a21837957c13f43389322e417e82c3 /target | |
| parent | i386: move hyperv_limits initialization to x86_cpu_realizefn() (diff) | |
| download | qemu-40399ecb6959ae696c235097c773d776392fde1f.tar.gz qemu-40399ecb6959ae696c235097c773d776392fde1f.tar.xz qemu-40399ecb6959ae696c235097c773d776392fde1f.zip | |
x86/cpu: Add AVX512_FP16 cpu feature
AVX512 Half-precision floating point (FP16) has better performance
compared to FP32 if the presicion or magnitude requirements are met.
It's defined as CPUID.(EAX=7,ECX=0):EDX[bit 23].
Refer to
https://software.intel.com/content/www/us/en/develop/download/\
intel-architecture-instruction-set-extensions-programming-reference.html
Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Message-Id: <20201216224002.32677-1-cathy.zhang@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/i386/cpu.c | 2 | ||||
| -rw-r--r-- | target/i386/cpu.h | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 45b0588af3..608e9cacf9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -979,7 +979,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "avx512-vp2intersect", NULL, "md-clear", NULL, NULL, NULL, "serialize", NULL, "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "avx512-fp16", NULL, NULL, "spec-ctrl", "stibp", NULL, "arch-capabilities", "core-capability", "ssbd", }, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ee03263800..9b2ced97ea 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -784,6 +784,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_SERIALIZE (1U << 14) /* TSX Suspend Load Address Tracking instruction */ #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) +/* AVX512_FP16 instruction */ +#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */ |