diff options
| author | Pavel Dovgalyuk | 2022-11-01 06:29:44 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2022-11-08 01:04:25 +0100 |
| commit | 4525ea7e0caa4aa6317204cd977179dea972cf6d (patch) | |
| tree | 7f8973dd706a751a9b138a7fc8cb77317da09648 /target | |
| parent | target/mips: Cast offset field of Octeon BBIT to int16_t (diff) | |
| download | qemu-4525ea7e0caa4aa6317204cd977179dea972cf6d.tar.gz qemu-4525ea7e0caa4aa6317204cd977179dea972cf6d.tar.xz qemu-4525ea7e0caa4aa6317204cd977179dea972cf6d.zip | |
target/mips: Enable LBX/LWX/* instructions for Octeon
This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/tcg/translate.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 2f2d707a12..4c4bd0823d 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -12173,12 +12173,16 @@ enum { #include "nanomips_translate.c.inc" /* MIPSDSP functions. */ -static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc, - int rd, int base, int offset) + +/* Indexed load is not for DSP only */ +static void gen_mips_lx(DisasContext *ctx, uint32_t opc, + int rd, int base, int offset) { TCGv t0; - check_dsp(ctx); + if (!(ctx->insn_flags & INSN_OCTEON)) { + check_dsp(ctx); + } t0 = tcg_temp_new(); if (base == 0) { @@ -14523,7 +14527,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_LBUX: case OPC_LHX: case OPC_LWX: - gen_mipsdsp_ld(ctx, op2, rd, rs, rt); + gen_mips_lx(ctx, op2, rd, rs, rt); break; default: /* Invalid */ MIPS_INVAL("MASK LX"); |