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| author | Artyom Tarasenko | 2016-06-10 10:44:15 +0200 |
|---|---|---|
| committer | Artyom Tarasenko | 2017-01-18 22:03:44 +0100 |
| commit | 5b5352b2f41e460f213a515e087c24dac1322f49 (patch) | |
| tree | 4539f613754ae5bae139b97de6402be1a15218ec /target | |
| parent | target-sparc: add UA2005 TTE bit #defines (diff) | |
| download | qemu-5b5352b2f41e460f213a515e087c24dac1322f49.tar.gz qemu-5b5352b2f41e460f213a515e087c24dac1322f49.tar.xz qemu-5b5352b2f41e460f213a515e087c24dac1322f49.zip | |
target-sparc: add UltraSPARC T1 TLB #defines
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/sparc/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4c4c159861..f65d8b5c1e 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -336,6 +336,10 @@ enum { #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) +/* UltraSPARC T1 specific */ +#define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ +#define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ + #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ |