diff options
| author | Richard Henderson | 2022-07-13 06:58:47 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-07-18 14:20:13 +0200 |
| commit | 6215113355a508c5e6d0a4337c79184d85eeed61 (patch) | |
| tree | 3682966446cc3a407684d2c2534e2dab2944ff7c /target | |
| parent | hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high (diff) | |
| download | qemu-6215113355a508c5e6d0a4337c79184d85eeed61.tar.gz qemu-6215113355a508c5e6d0a4337c79184d85eeed61.tar.xz qemu-6215113355a508c5e6d0a4337c79184d85eeed61.zip | |
target/arm: Fill in VL for tbflags when SME enabled and SVE disabled
When PSTATE.SM, VL = SVL even if SVE is disabled.
This is visible in kselftest ssve-test.
Reported-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220713045848.217364-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/helper.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index cfcad97ce0..6fff7fc64f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10882,13 +10882,19 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { int sme_el = sme_exception_el(env, el); + bool sm = FIELD_EX64(env->svcr, SVCR, SM); DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); if (sme_el == 0) { /* Similarly, do not compute SVL if SME is disabled. */ - DP_TBFLAG_A64(flags, SVL, sve_vqm1_for_el_sm(env, el, true)); + int svl = sve_vqm1_for_el_sm(env, el, true); + DP_TBFLAG_A64(flags, SVL, svl); + if (sm) { + /* If SVE is disabled, we will not have set VL above. */ + DP_TBFLAG_A64(flags, VL, svl); + } } - if (FIELD_EX64(env->svcr, SVCR, SM)) { + if (sm) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)); } |