diff options
| author | Yi Sun | 2016-12-14 03:50:03 +0100 |
|---|---|---|
| committer | Paolo Bonzini | 2016-12-22 16:00:25 +0100 |
| commit | 638cbd452d3a92a2ab18caee73078483d90f64eb (patch) | |
| tree | 8b612a8fccd4fa1e5c27b7409df5114a2e570fcd /target | |
| parent | block: drop remaining legacy aio functions in comment (diff) | |
| download | qemu-638cbd452d3a92a2ab18caee73078483d90f64eb.tar.gz qemu-638cbd452d3a92a2ab18caee73078483d90f64eb.tar.xz qemu-638cbd452d3a92a2ab18caee73078483d90f64eb.zip | |
target-i386: Add Intel SHA_NI instruction support.
Add SHA_NI feature bit. Its spec can be found at:
https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Message-Id: <1481683803-10051-1-git-send-email-yi.y.sun@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/i386/cpu.c | 2 | ||||
| -rw-r--r-- | target/i386/cpu.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index de1f30eeda..993f825e02 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -422,7 +422,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "avx512f", "avx512dq", "rdseed", "adx", "smap", "avx512ifma", "pcommit", "clflushopt", "clwb", NULL, "avx512pf", "avx512er", - "avx512cd", NULL, "avx512bw", "avx512vl", + "avx512cd", "sha-ni", "avx512bw", "avx512vl", }, .cpuid_eax = 7, .cpuid_needs_ecx = true, .cpuid_ecx = 0, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c605724022..d0bf62446b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -621,6 +621,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ +#define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ |