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| author | Weiwei Li | 2022-02-11 05:39:20 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-03-03 04:14:50 +0100 |
| commit | 6b1accefd4876ea5475d55454c7d5b52c02cb73c (patch) | |
| tree | 39a8d7f94395512a5ab98ab9ee1112120002d608 /target | |
| parent | target/riscv: add support for zhinx/zhinxmin (diff) | |
| download | qemu-6b1accefd4876ea5475d55454c7d5b52c02cb73c.tar.gz qemu-6b1accefd4876ea5475d55454c7d5b52c02cb73c.tar.xz qemu-6b1accefd4876ea5475d55454c7d5b52c02cb73c.zip | |
target/riscv: expose zfinx, zdinx, zhinx{min} properties
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 55371b1aa5..ddda4906ff 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -795,6 +795,11 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), + DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), + DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), + DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), + DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), + /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), |