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authorLaurent Vivier2017-01-13 19:36:33 +0100
committerLaurent Vivier2017-01-14 10:06:21 +0100
commit727d937b59f1f722f983e20f9cd23b0e7ef60165 (patch)
tree55e45a46b3a565b37798f8374c6cb763d3c2fb33 /target
parenttarget-m68k: CAS doesn't need aligned access (diff)
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target-m68k: increment/decrement with SP
On 680x0 family only. Address Register indirect With postincrement: When using the stack pointer (A7) with byte size data, the register is incremented by two. Address Register indirect With predecrement: When using the stack pointer (A7) with byte size data, the register is decremented by two. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-6-git-send-email-laurent@vivier.eu>
Diffstat (limited to 'target')
-rw-r--r--target/m68k/translate.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index cf5d8ddc3b..9f60fbc0db 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -725,7 +725,12 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
}
reg = get_areg(s, reg0);
tmp = tcg_temp_new();
- tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
+ if (reg0 == 7 && opsize == OS_BYTE &&
+ m68k_feature(s->env, M68K_FEATURE_M68000)) {
+ tcg_gen_subi_i32(tmp, reg, 2);
+ } else {
+ tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
+ }
return tmp;
case 5: /* Indirect displacement. */
reg = get_areg(s, reg0);
@@ -801,7 +806,12 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
result = gen_ldst(s, opsize, reg, val, what);
if (what == EA_STORE || !addrp) {
TCGv tmp = tcg_temp_new();
- tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
+ if (reg0 == 7 && opsize == OS_BYTE &&
+ m68k_feature(s->env, M68K_FEATURE_M68000)) {
+ tcg_gen_addi_i32(tmp, reg, 2);
+ } else {
+ tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
+ }
delay_set_areg(s, reg0, tmp, true);
}
return result;