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| author | Bin Meng | 2020-09-01 03:38:58 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:18 +0200 |
| commit | 73f6ed97acdbf7aec72d368fd5e16c00e04ac172 (patch) | |
| tree | b8e8f5ca6ba769ca3ac776411be5f2d75d72781b /target | |
| parent | hw/riscv: hart: Add a new 'resetvec' property (diff) | |
| download | qemu-73f6ed97acdbf7aec72d368fd5e16c00e04ac172.tar.gz qemu-73f6ed97acdbf7aec72d368fd5e16c00e04ac172.tar.xz qemu-73f6ed97acdbf7aec72d368fd5e16c00e04ac172.zip | |
target/riscv: cpu: Set reset vector based on the configured property value
Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f6aeecac15..57c006df5d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -139,7 +139,6 @@ static void riscv_any_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); - set_resetvec(env, DEFAULT_RSTVEC); } static void riscv_base_cpu_init(Object *obj) @@ -147,7 +146,6 @@ static void riscv_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, 0); - set_resetvec(env, DEFAULT_RSTVEC); } static void rvxx_sifive_u_cpu_init(Object *obj) @@ -155,7 +153,6 @@ static void rvxx_sifive_u_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, 0x1004); } static void rvxx_sifive_e_cpu_init(Object *obj) @@ -163,7 +160,6 @@ static void rvxx_sifive_e_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, 0x1004); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -174,7 +170,6 @@ static void rv32_ibex_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RV32 | RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, 0x8090); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -384,6 +379,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_feature(env, RISCV_FEATURE_PMP); } + set_resetvec(env, cpu->cfg.resetvec); + /* If misa isn't set (rv32 and rv64 machines) set it here */ if (!env->misa) { /* Do some ISA extension error checking */ |