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author | Richard Henderson | 2022-07-11 05:14:20 +0200 |
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committer | Peter Maydell | 2022-07-18 14:20:13 +0200 |
commit | 7f2cf760fe649972dba0948f8e3fc5618cb1fb37 (patch) | |
tree | 544f7f7d215d392eb88d75ff4a9be9d32507b45d /target | |
parent | target/arm: Fix aarch64_sve_change_el for SME (diff) | |
download | qemu-7f2cf760fe649972dba0948f8e3fc5618cb1fb37.tar.gz qemu-7f2cf760fe649972dba0948f8e3fc5618cb1fb37.tar.xz qemu-7f2cf760fe649972dba0948f8e3fc5618cb1fb37.zip |
linux-user/aarch64: Do not clear PROT_MTE on mprotect
The documentation for PROT_MTE says that it cannot be cleared
by mprotect. Further, the implementation of the VM_ARCH_CLEAR bit,
contains PROT_BTI confiming that bit should be cleared.
Introduce PAGE_TARGET_STICKY to allow target/arch/cpu.h to control
which bits may be reset during page_set_flags. This is sort of the
opposite of VM_ARCH_CLEAR, but works better with qemu's PAGE_* bits
that are separate from PROT_* bits.
Reported-by: Vitaly Buka <vitalybuka@google.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220711031420.17820-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/arm/cpu.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1e36a839ee..6afcc882f2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3392,9 +3392,12 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) /* * AArch64 usage of the PAGE_TARGET_* bits for linux-user. + * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect + * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. */ -#define PAGE_BTI PAGE_TARGET_1 -#define PAGE_MTE PAGE_TARGET_2 +#define PAGE_BTI PAGE_TARGET_1 +#define PAGE_MTE PAGE_TARGET_2 +#define PAGE_TARGET_STICKY PAGE_MTE #ifdef TARGET_TAGGED_ADDRESSES /** |