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authorAurelien Jarno2017-07-02 18:26:43 +0200
committerAurelien Jarno2017-07-18 23:39:15 +0200
commit82e8251374568ba63343b695925c883a7da3db6f (patch)
treea1a11033ab6e3dce2c1bf153dcea468e3871fdae /target
parenttarget/sh4: fix FPSCR cause vs flag inversion (diff)
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target/sh4: do not use a helper to implement fneg
There is no need to use a helper to flip one bit, just use a TCG xor instruction instead. Message-Id: <20170702202814.27793-5-aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target')
-rw-r--r--target/sh4/helper.h1
-rw-r--r--target/sh4/op_helper.c5
-rw-r--r--target/sh4/translate.c5
3 files changed, 2 insertions, 9 deletions
diff --git a/target/sh4/helper.h b/target/sh4/helper.h
index f715224822..d2398922dd 100644
--- a/target/sh4/helper.h
+++ b/target/sh4/helper.h
@@ -32,7 +32,6 @@ DEF_HELPER_FLAGS_2(float_DT, TCG_CALL_NO_WG, f64, env, i32)
DEF_HELPER_FLAGS_4(fmac_FT, TCG_CALL_NO_WG, f32, env, f32, f32, f32)
DEF_HELPER_FLAGS_3(fmul_FT, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fmul_DT, TCG_CALL_NO_WG, f64, env, f64, f64)
-DEF_HELPER_FLAGS_1(fneg_T, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_FLAGS_3(fsub_FT, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fsub_DT, TCG_CALL_NO_WG, f64, env, f64, f64)
DEF_HELPER_FLAGS_2(fsqrt_FT, TCG_CALL_NO_WG, f32, env, f32)
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index f2e39c5ca6..64206cf803 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -384,11 +384,6 @@ float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
return t0;
}
-float32 helper_fneg_T(float32 t0)
-{
- return float32_chs(t0);
-}
-
float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
{
set_float_exception_flags(0, &env->fp_status);
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index bff212a78e..9360522a98 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1691,9 +1691,8 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
CHECK_FPU_ENABLED
- {
- gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
- }
+ tcg_gen_xori_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)],
+ 0x80000000);
return;
case 0xf05d: /* fabs FRn/DRn - FPCSR: Nothing */
CHECK_FPU_ENABLED