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| author | Peter Maydell | 2017-01-20 12:15:07 +0100 |
|---|---|---|
| committer | Peter Maydell | 2017-01-20 12:15:07 +0100 |
| commit | 87a4b270348c69a446ebcddc039bfae31b1675cb (patch) | |
| tree | 7ad2361bb28a215bd210c80a7085cf7a1d9deefb /target | |
| parent | block: m25p80: Improve 1GiB Micron flash definition (diff) | |
| download | qemu-87a4b270348c69a446ebcddc039bfae31b1675cb.tar.gz qemu-87a4b270348c69a446ebcddc039bfae31b1675cb.tar.xz qemu-87a4b270348c69a446ebcddc039bfae31b1675cb.zip | |
target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32()
To run a VM in 32-bit EL1 our AArch32 interrupt handling code
needs to be able to cope with VIRQ and VFIQ exceptions.
These behave like IRQ and FIQ except that we don't need to try
to route them to Monitor mode.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/helper.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index b3875c7c6e..ba72ebbb07 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6399,6 +6399,20 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) } offset = 4; break; + case EXCP_VIRQ: + new_mode = ARM_CPU_MODE_IRQ; + addr = 0x18; + /* Disable IRQ and imprecise data aborts. */ + mask = CPSR_A | CPSR_I; + offset = 4; + break; + case EXCP_VFIQ: + new_mode = ARM_CPU_MODE_FIQ; + addr = 0x1c; + /* Disable FIQ, IRQ and imprecise data aborts. */ + mask = CPSR_A | CPSR_I | CPSR_F; + offset = 4; + break; case EXCP_SMC: new_mode = ARM_CPU_MODE_MON; addr = 0x08; |