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| author | Rebecca Cran | 2021-02-16 23:45:42 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-03-05 16:17:34 +0100 |
| commit | 89455d1ba6ed190e840cb732e63958755ea42a07 (patch) | |
| tree | 1a64307ecfb26f5936d2db2e2167accfcc5732bf /target | |
| parent | target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe (diff) | |
| download | qemu-89455d1ba6ed190e840cb732e63958755ea42a07.tar.gz qemu-89455d1ba6ed190e840cb732e63958755ea42a07.tar.xz qemu-89455d1ba6ed190e840cb732e63958755ea42a07.zip | |
target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU
Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210216224543.16142-3-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu64.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c255f1bcc3..f0a9e968c9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -674,6 +674,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64pfr1; t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* * Begin with full support for MTE. This will be downgraded to MTE=0 * during realize if the board provides no tag memory, much like @@ -723,6 +724,10 @@ static void aarch64_max_initfn(Object *obj) u = FIELD_DP32(u, ID_PFR0, DIT, 1); cpu->isar.id_pfr0 = u; + u = cpu->isar.id_pfr2; + u = FIELD_DP32(u, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 = u; + u = cpu->isar.id_mmfr3; u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->isar.id_mmfr3 = u; |