diff options
| author | LIU Zhiwei | 2022-01-20 13:20:33 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-01-21 06:52:57 +0100 |
| commit | 8c796f1a15d0fca41c4f3e985bfbd33a5afb9ddc (patch) | |
| tree | 54c8dc595799f212b8474d7adaeb0ed5acc39a4e /target | |
| parent | target/riscv: Create xl field in env (diff) | |
| download | qemu-8c796f1a15d0fca41c4f3e985bfbd33a5afb9ddc.tar.gz qemu-8c796f1a15d0fca41c4f3e985bfbd33a5afb9ddc.tar.xz qemu-8c796f1a15d0fca41c4f3e985bfbd33a5afb9ddc.zip | |
target/riscv: Ignore the pc bits above XLEN
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-7-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8ebcd57af0..d73925a823 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -43,7 +43,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, uint32_t flags = 0; - *pc = env->pc; + *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base = 0; if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { |