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authorArtyom Tarasenko2016-03-02 14:53:38 +0100
committerArtyom Tarasenko2017-01-18 22:03:44 +0100
commit9a10756d1204c3528e47892195349bf882069846 (patch)
treebb6b3067a56f7faffe2fd5d23a0a4f4d2504d0dd /target
parenttarget-sparc: implement UltraSPARC-T1 Strand status ASR (diff)
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target-sparc: hypervisor mode takes over nucleus mode
Accordinf to UA2005, 9.3.3 "Address Space Identifiers", "In hyperprivileged mode, all instruction fetches and loads and stores with implicit ASIs use a physical address, regardless of the value of TL". Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Diffstat (limited to 'target')
-rw-r--r--target/sparc/cpu.h4
-rw-r--r--target/sparc/translate.c6
2 files changed, 7 insertions, 3 deletions
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 9307b9135a..00fbb4ee1a 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -719,10 +719,10 @@ static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
: (env->lsu & DMMU_E) == 0) {
return MMU_PHYS_IDX;
- } else if (env->tl > 0) {
- return MMU_NUCLEUS_IDX;
} else if (cpu_hypervisor_mode(env)) {
return MMU_HYPV_IDX;
+ } else if (env->tl > 0) {
+ return MMU_NUCLEUS_IDX;
} else if (cpu_supervisor_mode(env)) {
return MMU_KERNEL_IDX;
} else {
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 8902e44ca2..009ea3ac92 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2142,7 +2142,11 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
case ASI_TWINX_NL:
case ASI_NUCLEUS_QUAD_LDD:
case ASI_NUCLEUS_QUAD_LDD_L:
- mem_idx = MMU_NUCLEUS_IDX;
+ if (hypervisor(dc)) {
+ mem_idx = MMU_HYPV_IDX;
+ } else {
+ mem_idx = MMU_NUCLEUS_IDX;
+ }
break;
case ASI_AIUP: /* As if user primary */
case ASI_AIUPL: /* As if user primary LE */