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| author | Joseph Myers | 2017-08-08 02:43:38 +0200 |
|---|---|---|
| committer | Paolo Bonzini | 2017-08-08 10:40:20 +0200 |
| commit | ab6ab3e9972a49a359f59895a88bed311472ca97 (patch) | |
| tree | 78e5a615953f63121bc978f5914457787d136d6b /target | |
| parent | scsi: clarify sense codes for LUN0 emulation (diff) | |
| download | qemu-ab6ab3e9972a49a359f59895a88bed311472ca97.tar.gz qemu-ab6ab3e9972a49a359f59895a88bed311472ca97.tar.xz qemu-ab6ab3e9972a49a359f59895a88bed311472ca97.zip | |
target/i386: set rip_offset for some SSE4.1 instructions
When emulating various SSE4.1 instructions such as pinsrd, the address
of a memory operand is computed without allowing for the 8-bit
immediate operand located after the memory operand, meaning that the
memory operand uses the wrong address in the case where it is
rip-relative. This patch adds the required rip_offset setting for
those instructions, so fixing some GCC test failures (13 in the gcc
testsuite in my GCC 6-based testing) when testing with a default CPU
setting enabling those instructions.
Signed-off-by: Joseph Myers <joseph@codesourcery.com>
Message-Id: <alpine.DEB.2.20.1708080041391.28702@digraph.polyomino.org.uk>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/i386/translate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/i386/translate.c b/target/i386/translate.c index cab9e32f91..5fdadf98cf 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4080,6 +4080,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (sse_fn_eppi == SSE_SPECIAL) { ot = mo_64_32(s->dflag); rm = (modrm & 7) | REX_B(s); + s->rip_offset = 1; if (mod != 3) gen_lea_modrm(env, s, modrm); reg = ((modrm >> 3) & 7) | rex_r; |