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| author | Edgar E. Iglesias | 2018-04-14 17:42:24 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias | 2018-05-29 09:35:14 +0200 |
| commit | ab6dd3808d52b96347a4595f9da77c46df1a5e1d (patch) | |
| tree | e45541bf83b2c4675b70c67d1f99b1271151ae43 /target | |
| parent | target-microblaze: dec_msr: Reuse more code when reg-decoding (diff) | |
| download | qemu-ab6dd3808d52b96347a4595f9da77c46df1a5e1d.tar.gz qemu-ab6dd3808d52b96347a4595f9da77c46df1a5e1d.tar.xz qemu-ab6dd3808d52b96347a4595f9da77c46df1a5e1d.zip | |
target-microblaze: dec_msr: Fix MTS to FSR
Fix moves to FSR. Not only bit 31 is accessible.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/microblaze/translate.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 6a270fbece..6f2cafa88a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -533,11 +533,9 @@ static void dec_msr(DisasContext *dc) break; case SR_EAR: case SR_ESR: + case SR_FSR: tcg_gen_mov_i32(cpu_SR[sr], cpu_R[dc->ra]); break; - case 0x7: - tcg_gen_andi_i32(cpu_SR[SR_FSR], cpu_R[dc->ra], 31); - break; case 0x800: tcg_gen_st_i32(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr)); |