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| author | Richard Henderson | 2022-10-24 12:49:27 +0200 |
|---|---|---|
| committer | Richard Henderson | 2022-10-26 03:11:28 +0200 |
| commit | ad1e84f5046c3dded43e0b056095938ce127a758 (patch) | |
| tree | 08900a573b9d2d82bc718c641c25a56caf552346 /target | |
| parent | target/ppc: Convert to tcg_ops restore_state_to_opc (diff) | |
| download | qemu-ad1e84f5046c3dded43e0b056095938ce127a758.tar.gz qemu-ad1e84f5046c3dded43e0b056095938ce127a758.tar.xz qemu-ad1e84f5046c3dded43e0b056095938ce127a758.zip | |
target/riscv: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e6d9c706bb..d14e95c9dc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -503,10 +503,14 @@ static bool riscv_cpu_has_work(CPUState *cs) #endif } -void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, - target_ulong *data) +static void riscv_restore_state_to_opc(CPUState *cs, + const TranslationBlock *tb, + const uint64_t *data) { + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); + if (xl == MXL_RV32) { env->pc = (int32_t)data[0]; } else { @@ -1138,6 +1142,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { static const struct TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, + .restore_state_to_opc = riscv_restore_state_to_opc, #ifndef CONFIG_USER_ONLY .tlb_fill = riscv_cpu_tlb_fill, |