diff options
| author | Alistair Francis | 2020-02-01 02:01:41 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2020-02-27 22:45:24 +0100 |
| commit | af1fa0039c799a350bcde07b3d8a71dfde07d11b (patch) | |
| tree | ff37ad821b9db32b5c5519ab366cd955b6fc3887 /target | |
| parent | target/riscv: Convert MIP CSR to target_ulong (diff) | |
| download | qemu-af1fa0039c799a350bcde07b3d8a71dfde07d11b.tar.gz qemu-af1fa0039c799a350bcde07b3d8a71dfde07d11b.tar.xz qemu-af1fa0039c799a350bcde07b3d8a71dfde07d11b.zip | |
target/riscv: Add the Hypervisor extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 95de9e58a2..010125efd6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,6 +67,7 @@ #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') +#define RVH RV('H') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there |