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| author | Peter Maydell | 2021-05-20 17:28:38 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-06-03 17:43:25 +0200 |
| commit | b26b5629c0be4a9539833de4189184a224590d14 (patch) | |
| tree | 6ba883e488bf82896ec16e9cf518f7b3f2fe8369 /target | |
| parent | target/arm: Implement M-profile VPR register (diff) | |
| download | qemu-b26b5629c0be4a9539833de4189184a224590d14.tar.gz qemu-b26b5629c0be4a9539833de4189184a224590d14.tar.xz qemu-b26b5629c0be4a9539833de4189184a224590d14.zip | |
target/arm: Make FPSCR.LTPSIZE writable for MVE
The M-profile FPSCR has an LTPSIZE field, but if MVE is not
implemented it is read-only and always reads as 4; this is how QEMU
currently handles it.
Make the field writable when MVE is implemented.
We can safely add the field to the MVE migration struct because
currently no CPUs enable MVE and so the migration struct is never
used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-8-peter.maydell@linaro.org
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu.h | 3 | ||||
| -rw-r--r-- | target/arm/machine.c | 1 | ||||
| -rw-r--r-- | target/arm/vfp_helper.c | 9 |
3 files changed, 9 insertions, 4 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df2f189c49..c389b1e969 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -563,7 +563,7 @@ typedef struct CPUARMState { uint32_t fpdscr[M_REG_NUM_BANKS]; uint32_t cpacr[M_REG_NUM_BANKS]; uint32_t nsacr; - int ltpsize; + uint32_t ltpsize; uint32_t vpr; } v7m; @@ -1562,6 +1562,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) +#define FPCR_LTPSIZE_LENGTH 3 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) diff --git a/target/arm/machine.c b/target/arm/machine.c index 62a71a3b64..81e30de824 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -332,6 +332,7 @@ static const VMStateDescription vmstate_m_mve = { .needed = mve_needed, .fields = (VMStateField[]) { VMSTATE_UINT32(env.v7m.vpr, ARMCPU), + VMSTATE_UINT32(env.v7m.ltpsize, ARMCPU), VMSTATE_END_OF_LIST() }, }; diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 01b9d8557f..e0886ab5a5 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -195,8 +195,10 @@ uint32_t vfp_get_fpscr(CPUARMState *env) void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { + ARMCPU *cpu = env_archcpu(env); + /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(any_fp16, env_archcpu(env))) { + if (!cpu_isar_feature(any_fp16, cpu)) { val &= ~FPCR_FZ16; } @@ -210,11 +212,12 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) * because in v7A no-short-vector-support cores still had to * allow Stride/Len to be written with the only effect that * some insns are required to UNDEF if the guest sets them. - * - * TODO: if M-profile MVE implemented, set LTPSIZE. */ env->vfp.vec_len = extract32(val, 16, 3); env->vfp.vec_stride = extract32(val, 20, 2); + } else if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT, + FPCR_LTPSIZE_LENGTH); } if (arm_feature(env, ARM_FEATURE_NEON)) { |