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| author | Rui Wang | 2022-11-04 05:05:16 +0100 |
|---|---|---|
| committer | Song Gao | 2022-11-04 10:10:52 +0100 |
| commit | b4bda2006f482f778d9dbf86038ff115fe89db92 (patch) | |
| tree | 0aede78e9c1b850185cca8bd59ce3b2156834238 /target | |
| parent | target/loongarch: Fix raise_mmu_exception() set wrong exception_index (diff) | |
| download | qemu-b4bda2006f482f778d9dbf86038ff115fe89db92.tar.gz qemu-b4bda2006f482f778d9dbf86038ff115fe89db92.tar.xz qemu-b4bda2006f482f778d9dbf86038ff115fe89db92.zip | |
target/loongarch: Adjust the layout of hardware flags bit fields
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221104040517.222059-2-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Diffstat (limited to 'target')
| -rw-r--r-- | target/loongarch/cpu.h | 9 | ||||
| -rw-r--r-- | target/loongarch/insn_trans/trans_privileged.c.inc | 2 | ||||
| -rw-r--r-- | target/loongarch/translate.c | 6 |
3 files changed, 14 insertions, 3 deletions
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index dbce176564..f482ad94fe 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -14,6 +14,7 @@ #include "qemu/timer.h" #include "exec/memory.h" #include "hw/sysbus.h" +#include "cpu-csr.h" #define IOCSRF_TEMP 0 #define IOCSRF_NODECNT 1 @@ -391,6 +392,12 @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) #endif } +/* + * LoongArch CPUs hardware flags. + */ +#define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */ +#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ + static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, target_ulong *pc, target_ulong *cs_base, @@ -398,7 +405,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, { *pc = env->pc; *cs_base = 0; - *flags = cpu_mmu_index(env, false); + *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); } void loongarch_cpu_list(void); diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc index 9c4dcbfcfb..ff3a6d95ae 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -159,7 +159,7 @@ static const CSRInfo csr_info[] = { static bool check_plv(DisasContext *ctx) { - if (ctx->base.tb->flags == MMU_USER_IDX) { + if (ctx->mem_idx == MMU_USER_IDX) { generate_exception(ctx, EXCCODE_IPE); return true; } diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 6091772349..31462b2b61 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -75,7 +75,11 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase, DisasContext *ctx = container_of(dcbase, DisasContext, base); ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK; - ctx->mem_idx = ctx->base.tb->flags; + if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) { + ctx->mem_idx = ctx->base.tb->flags & HW_FLAGS_PLV_MASK; + } else { + ctx->mem_idx = MMU_DA_IDX; + } /* Bound the number of insns to execute to those left on the page. */ bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; |