diff options
| author | Peter Maydell | 2020-11-19 22:56:06 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-12-10 12:44:56 +0100 |
| commit | be9500bb17e1266ac5505a50c198397e16a56de4 (patch) | |
| tree | 99724446bd4b78e3f8563240c17d1f4e2cae42ce /target | |
| parent | target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry (diff) | |
| download | qemu-be9500bb17e1266ac5505a50c198397e16a56de4.tar.gz qemu-be9500bb17e1266ac5505a50c198397e16a56de4.tar.xz qemu-be9500bb17e1266ac5505a50c198397e16a56de4.zip | |
target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures
In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule
R_LLRP). (In previous versions of the architecture this was either
required or IMPDEF.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-18-peter.maydell@linaro.org
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/m_helper.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 721b4b4896..9cdc8a64c2 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -722,11 +722,15 @@ load_fail: * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are * secure); otherwise it targets the same security state as the * underlying exception. + * In v8.1M HardFaults from vector table fetch fails don't set FORCED. */ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { exc_secure = true; } - env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK; + env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK; + if (!arm_feature(env, ARM_FEATURE_V8_1M)) { + env->v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; + } armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure); return false; } |