diff options
| author | Alex Bennée | 2018-03-01 12:05:56 +0100 |
|---|---|---|
| committer | Peter Maydell | 2018-03-01 12:13:59 +0100 |
| commit | c625ff95070e3ef96bd007de744e1d97c881efeb (patch) | |
| tree | 683434710d4dd9b4d69f3fa028eaead9432544ba /target | |
| parent | arm/helper.c: re-factor rsqrte and add rsqrte_f16 (diff) | |
| download | qemu-c625ff95070e3ef96bd007de744e1d97c881efeb.tar.gz qemu-c625ff95070e3ef96bd007de744e1d97c881efeb.tar.xz qemu-c625ff95070e3ef96bd007de744e1d97c881efeb.zip | |
arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-28-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate-a64.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1096ff48ac..86231b33bb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11388,6 +11388,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ need_fpst = false; break; + case 0x7d: /* FRSQRTE */ case 0x7f: /* FSQRT (vector) */ break; default: @@ -11452,6 +11453,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); + break; default: g_assert_not_reached(); } @@ -11504,6 +11508,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x7f: /* FSQRT */ gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus); break; |