diff options
| author | Mark Cave-Ayland | 2022-09-17 13:25:15 +0200 |
|---|---|---|
| committer | Laurent Vivier | 2022-09-21 15:10:57 +0200 |
| commit | c7546abfaa1b1c2729eaddd41c6268a73cdae14f (patch) | |
| tree | 8f20d53103e4802e4eceed82769803d32b622feb /target | |
| parent | target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K (diff) | |
| download | qemu-c7546abfaa1b1c2729eaddd41c6268a73cdae14f.tar.gz qemu-c7546abfaa1b1c2729eaddd41c6268a73cdae14f.tar.xz qemu-c7546abfaa1b1c2729eaddd41c6268a73cdae14f.zip | |
target/m68k: always call gen_exit_tb() after writes to SR
Any write to SR can change the security state so always call gen_exit_tb() when
this occurs. In particular MacOS makes use of andiw/oriw in a few places to
handle the switch between user and supervisor mode.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220917112515.83905-5-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'target')
| -rw-r--r-- | target/m68k/translate.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 0b618e8eb2..233b9d8e57 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2375,6 +2375,7 @@ DISAS_INSN(arith_im) tcg_gen_or_i32(dest, src1, im); if (with_SR) { gen_set_sr(s, dest, opsize == OS_BYTE); + gen_exit_tb(s); } else { DEST_EA(env, insn, opsize, dest, &addr); gen_logic_cc(s, dest, opsize); @@ -2384,6 +2385,7 @@ DISAS_INSN(arith_im) tcg_gen_and_i32(dest, src1, im); if (with_SR) { gen_set_sr(s, dest, opsize == OS_BYTE); + gen_exit_tb(s); } else { DEST_EA(env, insn, opsize, dest, &addr); gen_logic_cc(s, dest, opsize); @@ -2407,6 +2409,7 @@ DISAS_INSN(arith_im) tcg_gen_xor_i32(dest, src1, im); if (with_SR) { gen_set_sr(s, dest, opsize == OS_BYTE); + gen_exit_tb(s); } else { DEST_EA(env, insn, opsize, dest, &addr); gen_logic_cc(s, dest, opsize); @@ -4614,6 +4617,7 @@ DISAS_INSN(strldsr) } gen_push(s, gen_get_sr(s)); gen_set_sr_im(s, ext, 0); + gen_exit_tb(s); } DISAS_INSN(move_from_sr) |