diff options
| author | Artyom Tarasenko | 2016-11-01 21:57:01 +0100 |
|---|---|---|
| committer | Artyom Tarasenko | 2017-01-18 22:03:44 +0100 |
| commit | c9b459aab8c5775a21dd913fc8820b736181e7be (patch) | |
| tree | 41948f34dfda9cd68bfcff46c48319c87a6fe1d1 /target | |
| parent | target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode (diff) | |
| download | qemu-c9b459aab8c5775a21dd913fc8820b736181e7be.tar.gz qemu-c9b459aab8c5775a21dd913fc8820b736181e7be.tar.xz qemu-c9b459aab8c5775a21dd913fc8820b736181e7be.zip | |
target-sparc: store cpu super- and hypervisor flags in TB
Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/sparc/cpu.h | 17 | ||||
| -rw-r--r-- | target/sparc/translate.c | 24 |
2 files changed, 36 insertions, 5 deletions
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index e815a1949b..1e65c94e2d 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -670,6 +670,11 @@ static inline int cpu_supervisor_mode(CPUSPARCState *env1) { return env1->pstate & PS_PRIV; } +#else +static inline int cpu_supervisor_mode(CPUSPARCState *env1) +{ + return env1->psrs; +} #endif static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) @@ -736,6 +741,8 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_MMU_MASK 7 #define TB_FLAG_FPU_ENABLED (1 << 4) #define TB_FLAG_AM_ENABLED (1 << 5) +#define TB_FLAG_SUPER (1 << 6) +#define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, @@ -745,7 +752,17 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, *pc = env->pc; *cs_base = env->npc; flags = cpu_mmu_index(env, false); +#ifndef CONFIG_USER_ONLY + if (cpu_supervisor_mode(env)) { + flags |= TB_FLAG_SUPER; + } +#endif #ifdef TARGET_SPARC64 +#ifndef CONFIG_USER_ONLY + if (cpu_hypervisor_mode(env)) { + flags |= TB_FLAG_HYPER; + } +#endif if (env->pstate & PS_AM) { flags |= TB_FLAG_AM_ENABLED; } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ead585eef5..729f4e27ee 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -72,9 +72,16 @@ typedef struct DisasContext { target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ int is_br; int mem_idx; - int fpu_enabled; - int address_mask_32bit; - int singlestep; + bool fpu_enabled; + bool address_mask_32bit; + bool singlestep; +#ifndef CONFIG_USER_ONLY + bool supervisor; +#ifdef TARGET_SPARC64 + bool hypervisor; +#endif +#endif + uint32_t cc_op; /* current CC operation */ struct TranslationBlock *tb; sparc_def_t *def; @@ -283,10 +290,11 @@ static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs) #define hypervisor(dc) 0 #endif #else -#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX) #ifdef TARGET_SPARC64 -#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX) +#define hypervisor(dc) (dc->hypervisor) +#define supervisor(dc) (dc->supervisor | dc->hypervisor) #else +#define supervisor(dc) (dc->supervisor) #endif #endif @@ -5710,9 +5718,15 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) dc->fpu_enabled = tb_fpu_enabled(tb->flags); dc->address_mask_32bit = tb_am_enabled(tb->flags); dc->singlestep = (cs->singlestep_enabled || singlestep); +#ifndef CONFIG_USER_ONLY + dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0; +#endif #ifdef TARGET_SPARC64 dc->fprs_dirty = 0; dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; +#ifndef CONFIG_USER_ONLY + dc->hypervisor = (tb->flags & TB_FLAG_HYPER) != 0; +#endif #endif num_insns = 0; |