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authorWeiwei Li2022-04-23 04:35:10 +0200
committerAlistair Francis2022-04-29 02:47:45 +0200
commitcf7ed971ae6f4e3683340b890a2db664a88cd896 (patch)
tree87065af097f0748a208a0a47cd42dc1766c31c6e /target
parentdisas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions (diff)
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target/riscv: rvk: expose zbk* and zk* properties
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-15-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r--target/riscv/cpu.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 62a47c197b..dff4606585 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -849,7 +849,20 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+ DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
+ DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
+ DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
+ DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
+ DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
+ DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
+ DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
+ DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
+ DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
+ DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
+ DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
+ DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),