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| author | Stephane Duverger | 2020-12-09 18:35:35 +0100 |
|---|---|---|
| committer | David Gibson | 2020-12-14 05:54:12 +0100 |
| commit | d55dfd446cd58b36f1b58d178039d7657a50e803 (patch) | |
| tree | 980046959342b203531e46c18bb2a9a8aed57207 /target | |
| parent | ppc/e500: Free irqs array to avoid memleak (diff) | |
| download | qemu-d55dfd446cd58b36f1b58d178039d7657a50e803.tar.gz qemu-d55dfd446cd58b36f1b58d178039d7657a50e803.tar.xz qemu-d55dfd446cd58b36f1b58d178039d7657a50e803.zip | |
ppc/translate: Use POWERPC_MMU_64 to detect 64-bit MMU models
The ppc_tr_init_disas_context() function currently checks whether the
MMU is 64-bit by ANDing its model type with POWERPC_MMU_64B. This is
wrong : POWERPC_MMU_64B isn't a mask, it is the generic MMU model for
pre-PowerISA-2.03 64-bit CPUs (ie. PowerPC 970 in QEMU).
Use POWERPC_MMU_64 instead of POWERPC_MMU_64B. This should fix a
potential bug with some 32-bit CPUs for which 'need_access_type'
was mis-computed because (POWERPC_MMU_32B & POWERPC_MMU_64B)
happens to be equal to 1. The end result being a crash in
ppc_hash32_direct_store() because the access type isn't set:
cpu_abort(cs, "ERROR: instruction should not need "
"address translation\n");
This doesn't change anything for 'lazy_tlb_flush' since POWERPC_MMU_32B
is checked first.
Fixes: 5f2a6254522b ("ppc: Don't set access_type on all load/stores on hash64")
Signed-off-by: Stephane Duverger <stephane.duverger@free.fr>
[groug: - extended patch to address another misuse of POWERPC_MMU_64B
- updated title and changelog accordingly]
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <20201209173536.1437351-2-groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 54cac0e6a7..e68dd65ad3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7892,7 +7892,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->insns_flags = env->insns_flags; ctx->insns_flags2 = env->insns_flags2; ctx->access_type = -1; - ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); + ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64); ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; ctx->flags = env->flags; @@ -7902,7 +7902,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #endif ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B || env->mmu_model == POWERPC_MMU_601 - || (env->mmu_model & POWERPC_MMU_64B); + || env->mmu_model & POWERPC_MMU_64; ctx->fpu_enabled = !!msr_fp; if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) { |