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authorPavel Zbitskiy2018-08-21 04:51:00 +0200
committerCornelia Huck2018-08-28 17:37:01 +0200
commitdc95b31dac65adb92256e67a5f0fc88ab37404c2 (patch)
tree09829edb988fd5fbb174dc1597e9baad713b3103 /target
parenttarget/s390x: add BAL and BALR instructions (diff)
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target/s390x: fix CSST decoding and runtime alignment check
CSST is defined as: C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0) It means that the first parameter is handled by in1_la1(). in1_la1() fills addr1 field, and not in1. Furthermore, when extract32() is used for the alignment check, the third parameter should specify the number of trailing bits that must be 0. For FC these numbers are: FC=0 (word, 4 bytes): 2 FC=1 (double word, 8 bytes): 3 FC=2 (quad word, 16 bytes): 4 For SC these numbers correspond to the size: SC=0: 0 SC=1: 1 SC=2: 2 SC=3: 3 SC=4: 4 Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-4-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'target')
-rw-r--r--target/s390x/mem_helper.c2
-rw-r--r--target/s390x/translate.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index e21a47fb4d..c94dbf3fcb 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1442,7 +1442,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
}
/* Sanity check the alignments. */
- if (extract32(a1, 0, 4 << fc) || extract32(a2, 0, 1 << sc)) {
+ if (extract32(a1, 0, fc + 2) || extract32(a2, 0, sc)) {
goto spec_exception;
}
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 9caae5af84..4f62a38c97 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -2058,9 +2058,9 @@ static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
TCGv_i32 t_r3 = tcg_const_i32(r3);
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
- gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->in1, o->in2);
+ gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->addr1, o->in2);
} else {
- gen_helper_csst(cc_op, cpu_env, t_r3, o->in1, o->in2);
+ gen_helper_csst(cc_op, cpu_env, t_r3, o->addr1, o->in2);
}
tcg_temp_free_i32(t_r3);