diff options
| author | Bin Meng | 2019-08-08 04:49:30 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-09-17 17:42:43 +0200 |
| commit | ddf781322820b6ea174fbe43ddc6a95e8cac8051 (patch) | |
| tree | 6126c8f36a9e33b15072018147604f0dbffdf926 /target | |
| parent | target/riscv: Update the Hypervisor CSRs to v0.4 (diff) | |
| download | qemu-ddf781322820b6ea174fbe43ddc6a95e8cac8051.tar.gz qemu-ddf781322820b6ea174fbe43ddc6a95e8cac8051.tar.xz qemu-ddf781322820b6ea174fbe43ddc6a95e8cac8051.zip | |
riscv: rv32: Root page table address can be larger than 32-bit
For RV32, the root page table's PPN has 22 bits hence its address
bits could be larger than the maximum bits that target_ulong is
able to represent. Use hwaddr instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu_helper.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 96373b67d8..87dd6a6ece 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -186,12 +186,12 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, *prot = 0; - target_ulong base; + hwaddr base; int levels, ptidxbits, ptesize, vm, sum; int mxr = get_field(env->mstatus, MSTATUS_MXR); if (env->priv_ver >= PRIV_VERSION_1_10_0) { - base = get_field(env->satp, SATP_PPN) << PGSHIFT; + base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; sum = get_field(env->mstatus, MSTATUS_SUM); vm = get_field(env->satp, SATP_MODE); switch (vm) { @@ -211,7 +211,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, g_assert_not_reached(); } } else { - base = env->sptbr << PGSHIFT; + base = (hwaddr)(env->sptbr) << PGSHIFT; sum = !get_field(env->mstatus, MSTATUS_PUM); vm = get_field(env->mstatus, MSTATUS_VM); switch (vm) { @@ -249,7 +249,7 @@ restart: ((1 << ptidxbits) - 1); /* check that physical address of PTE is legal */ - target_ulong pte_addr = base + idx * ptesize; + hwaddr pte_addr = base + idx * ptesize; if (riscv_feature(env, RISCV_FEATURE_PMP) && !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), @@ -261,7 +261,7 @@ restart: #elif defined(TARGET_RISCV64) target_ulong pte = ldq_phys(cs->as, pte_addr); #endif - target_ulong ppn = pte >> PTE_PPN_SHIFT; + hwaddr ppn = pte >> PTE_PPN_SHIFT; if (!(pte & PTE_V)) { /* Invalid PTE */ |