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| author | Peter Maydell | 2021-01-08 20:51:57 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-01-12 22:19:02 +0100 |
| commit | e4d51ac6921dc861bfb3d20e4c7dcf345840a9da (patch) | |
| tree | c6ddb6d408f8eb89d697ce5a6b03b6b52a848902 /target | |
| parent | docs: Add qemu-storage-daemon(1) manpage to meson.build (diff) | |
| download | qemu-e4d51ac6921dc861bfb3d20e4c7dcf345840a9da.tar.gz qemu-e4d51ac6921dc861bfb3d20e4c7dcf345840a9da.tar.xz qemu-e4d51ac6921dc861bfb3d20e4c7dcf345840a9da.zip | |
target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
In commit cd8be50e58f63413c0 we converted the A32 coprocessor
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
because it moved the handling of "cp insns which are handled
by looking up the cp register in the hashtable" from after the
call to the legacy disas_xscale_insn() decode to before it,
with the result that all XScale/iWMMXt insns now UNDEF.
Update valid_cp() so that it knows that on XScale cp 0 and 1
are not standard coprocessor instructions; this will cause
the decodetree trans_ functions to ignore them, so that
execution will correctly get through to the legacy decode again.
Cc: qemu-stable@nongnu.org
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index f5acd32e76..528b93dffa 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5282,7 +5282,14 @@ static bool valid_cp(DisasContext *s, int cp) * only cp14 and cp15 are valid, and other values aren't considered * to be in the coprocessor-instruction space at all. v8M still * permits coprocessors 0..7. + * For XScale, we must not decode the XScale cp0, cp1 space as + * a standard coprocessor insn, because we want to fall through to + * the legacy disas_xscale_insn() decoder after decodetree is done. */ + if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) { + return false; + } + if (arm_dc_feature(s, ARM_FEATURE_V8) && !arm_dc_feature(s, ARM_FEATURE_M)) { return cp >= 14; |