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| author | Richard Henderson | 2022-06-21 22:47:20 +0200 |
|---|---|---|
| committer | Richard Henderson | 2022-06-21 22:47:20 +0200 |
| commit | f200ff158d5abcb974a6b597a962b6b2fbea2b06 (patch) | |
| tree | 0bad1924d9b2c6ccb7c816a530fe7d5ee76c97b0 /target | |
| parent | Merge tag 'pull-ppc-20220621' of https://gitlab.com/danielhb/qemu into staging (diff) | |
| parent | util/cacheflush: Optimize flushing when ppc host has coherent icache (diff) | |
| download | qemu-f200ff158d5abcb974a6b597a962b6b2fbea2b06.tar.gz qemu-f200ff158d5abcb974a6b597a962b6b2fbea2b06.tar.xz qemu-f200ff158d5abcb974a6b597a962b6b2fbea2b06.zip | |
Merge tag 'pull-tcg-20220621' of https://gitlab.com/rth7680/qemu into staging
Speed empty timer list in qemu_clock_deadline_ns_all.
Implement remainder for Power3.1 hosts.
Optimize ppc host icache flushing.
Cleanups to tcg_accel_ops_init.
Fix mmio crash accessing unmapped physical memory.
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# gpg: Signature made Tue 21 Jun 2022 01:45:31 PM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
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# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20220621' of https://gitlab.com/rth7680/qemu:
util/cacheflush: Optimize flushing when ppc host has coherent icache
util/cacheflush: Merge aarch64 ctr_el0 usage
util: Merge cacheflush.c and cacheinfo.c
softmmu: Always initialize xlat in address_space_translate_for_iotlb
qemu-timer: Skip empty timer lists before locking in qemu_clock_deadline_ns_all
accel/tcg: Reorganize tcg_accel_ops_init()
accel/tcg: Init TCG cflags in vCPU thread handler
target/avr: Drop avr_cpu_memory_rw_debug()
tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/avr/cpu.c | 1 | ||||
| -rw-r--r-- | target/avr/cpu.h | 2 | ||||
| -rw-r--r-- | target/avr/helper.c | 6 |
3 files changed, 0 insertions, 9 deletions
diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5d70e34dd5..05b992ff73 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -214,7 +214,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->has_work = avr_cpu_has_work; cc->dump_state = avr_cpu_dump_state; cc->set_pc = avr_cpu_set_pc; - cc->memory_rw_debug = avr_cpu_memory_rw_debug; dc->vmsd = &vms_avr_cpu; cc->sysemu_ops = &avr_sysemu_ops; cc->disas_set_info = avr_cpu_disas_set_info; diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d304f33301..96419c0c2b 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -184,8 +184,6 @@ void avr_cpu_tcg_init(void); void avr_cpu_list(void); int cpu_avr_exec(CPUState *cpu); -int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, - int len, bool is_write); enum { TB_FLAGS_FULL_ACCESS = 1, diff --git a/target/avr/helper.c b/target/avr/helper.c index c27f702901..db76452f9a 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -93,12 +93,6 @@ void avr_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; } -int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, - int len, bool is_write) -{ - return cpu_memory_rw_debug(cs, addr, buf, len, is_write); -} - hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { return addr; /* I assume 1:1 address correspondence */ |