Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging

QOM boilerplate cleanup

Documentation build fix:
* memory: Remove kernel-doc comment marker (Eduardo Habkost)

QOM cleanups:
* Rename QOM macros for consistency between
  TYPE_* and type checking constants (Eduardo Habkost)

QOM new macros:
* OBJECT_DECLARE_* and OBJECT_DEFINE_* macros (Daniel P. Berrangé)
* DECLARE_*_CHECKER macros (Eduardo Habkost)

Automated QOM boilerplate changes:
* Automated changes to use DECLARE_*_CHECKER (Eduardo Habkost
* Automated changes to use OBJECT_DECLARE* (Eduardo Habkost)

# gpg: Signature made Thu 10 Sep 2020 19:17:49 BST
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/machine-next-pull-request: (33 commits)
  virtio-vga: Use typedef name for instance_size
  vhost-user-vga: Use typedef name for instance_size
  xilinx_axienet: Use typedef name for instance_size
  lpc_ich9: Use typedef name for instance_size
  omap_intc: Use typedef name for instance_size
  xilinx_axidma: Use typedef name for instance_size
  tusb6010: Rename TUSB to TUSB6010
  pc87312: Rename TYPE_PC87312_SUPERIO to TYPE_PC87312
  vfio: Rename PCI_VFIO to VFIO_PCI
  usb: Rename USB_SERIAL_DEV to USB_SERIAL
  sabre: Rename SABRE_DEVICE to SABRE
  rs6000_mc: Rename RS6000MC_DEVICE to RS6000MC
  filter-rewriter: Rename FILTER_COLO_REWRITER to FILTER_REWRITER
  esp: Rename ESP_STATE to ESP
  ahci: Rename ICH_AHCI to ICH9_AHCI
  vmgenid: Rename VMGENID_DEVICE to TYPE_VMGENID
  vfio: Rename VFIO_AP_DEVICE_TYPE to TYPE_VFIO_AP_DEVICE
  dev-smartcard-reader: Rename CCID_DEV_NAME to TYPE_USB_CCID_DEV
  ap-device: Rename AP_DEVICE_TYPE to TYPE_AP_DEVICE
  gpex: Fix type checking function name
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

26 files changed, 142 insertions, 235 deletions

diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
index 08832fa767..568fe3fb77 100644
--- a/target/alpha/cpu-qom.h
+++ b/target/alpha/cpu-qom.h
@@ -21,15 +21,12 @@
 #define QEMU_ALPHA_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #define TYPE_ALPHA_CPU "alpha-cpu"
 
-#define ALPHA_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(AlphaCPUClass, (klass), TYPE_ALPHA_CPU)
-#define ALPHA_CPU(obj) \
-    OBJECT_CHECK(AlphaCPU, (obj), TYPE_ALPHA_CPU)
-#define ALPHA_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(AlphaCPUClass, (obj), TYPE_ALPHA_CPU)
+OBJECT_DECLARE_TYPE(AlphaCPU, AlphaCPUClass,
+                    alpha_cpu, ALPHA_CPU)
 
 /**
  * AlphaCPUClass:
@@ -38,15 +35,14 @@
  *
  * An Alpha CPU model.
  */
-typedef struct AlphaCPUClass {
+struct AlphaCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} AlphaCPUClass;
+};
 
-typedef struct AlphaCPU AlphaCPU;
 
 #endif
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index fdef05cacf..94bbbd4473 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -21,17 +21,14 @@
 #define QEMU_ARM_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 struct arm_boot_info;
 
 #define TYPE_ARM_CPU "arm-cpu"
 
-#define ARM_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
-#define ARM_CPU(obj) \
-    OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
-#define ARM_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
+OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass,
+                    arm_cpu, ARM_CPU)
 
 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
 
@@ -51,7 +48,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info);
  *
  * An ARM CPU model.
  */
-typedef struct ARMCPUClass {
+struct ARMCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
@@ -59,21 +56,19 @@ typedef struct ARMCPUClass {
     const ARMCPUInfo *info;
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} ARMCPUClass;
+};
 
-typedef struct ARMCPU ARMCPU;
 
 #define TYPE_AARCH64_CPU "aarch64-cpu"
-#define AARCH64_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
-#define AARCH64_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AARCH64_CPU)
+typedef struct AArch64CPUClass AArch64CPUClass;
+DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
+                       TYPE_AARCH64_CPU)
 
-typedef struct AArch64CPUClass {
+struct AArch64CPUClass {
     /*< private >*/
     ARMCPUClass parent_class;
     /*< public >*/
-} AArch64CPUClass;
+};
 
 void register_cp_regs_for_features(ARMCPU *cpu);
 void init_cpreg_list(ARMCPU *cpu);
diff --git a/target/arm/idau.h b/target/arm/idau.h
index 7c0e4e3776..0ef5251971 100644
--- a/target/arm/idau.h
+++ b/target/arm/idau.h
@@ -33,16 +33,15 @@
 #define TYPE_IDAU_INTERFACE "idau-interface"
 #define IDAU_INTERFACE(obj) \
     INTERFACE_CHECK(IDAUInterface, (obj), TYPE_IDAU_INTERFACE)
-#define IDAU_INTERFACE_CLASS(class) \
-    OBJECT_CLASS_CHECK(IDAUInterfaceClass, (class), TYPE_IDAU_INTERFACE)
-#define IDAU_INTERFACE_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(IDAUInterfaceClass, (obj), TYPE_IDAU_INTERFACE)
+typedef struct IDAUInterfaceClass IDAUInterfaceClass;
+DECLARE_CLASS_CHECKERS(IDAUInterfaceClass, IDAU_INTERFACE,
+                       TYPE_IDAU_INTERFACE)
 
 typedef struct IDAUInterface IDAUInterface;
 
 #define IREGION_NOTVALID -1
 
-typedef struct IDAUInterfaceClass {
+struct IDAUInterfaceClass {
     InterfaceClass parent;
 
     /* Check the specified address and return the IDAU security information
@@ -54,6 +53,6 @@ typedef struct IDAUInterfaceClass {
      */
     void (*check)(IDAUInterface *ii, uint32_t address, int *iregion,
                   bool *exempt, bool *ns, bool *nsc);
-} IDAUInterfaceClass;
+};
 
 #endif
diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
index d23ad43a99..49d63faad2 100644
--- a/target/avr/cpu-qom.h
+++ b/target/avr/cpu-qom.h
@@ -22,15 +22,12 @@
 #define QEMU_AVR_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #define TYPE_AVR_CPU "avr-cpu"
 
-#define AVR_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(AVRCPUClass, (klass), TYPE_AVR_CPU)
-#define AVR_CPU(obj) \
-    OBJECT_CHECK(AVRCPU, (obj), TYPE_AVR_CPU)
-#define AVR_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(AVRCPUClass, (obj), TYPE_AVR_CPU)
+OBJECT_DECLARE_TYPE(AVRCPU, AVRCPUClass,
+                    avr_cpu, AVR_CPU)
 
 /**
  *  AVRCPUClass:
@@ -40,14 +37,13 @@
  *
  *  A AVR CPU model.
  */
-typedef struct AVRCPUClass {
+struct AVRCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} AVRCPUClass;
+};
 
-typedef struct AVRCPU AVRCPU;
 
 #endif /* !defined (QEMU_AVR_CPU_QOM_H) */
diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
index f1de6041dc..2b0328113c 100644
--- a/target/cris/cpu-qom.h
+++ b/target/cris/cpu-qom.h
@@ -21,15 +21,12 @@
 #define QEMU_CRIS_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #define TYPE_CRIS_CPU "cris-cpu"
 
-#define CRIS_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(CRISCPUClass, (klass), TYPE_CRIS_CPU)
-#define CRIS_CPU(obj) \
-    OBJECT_CHECK(CRISCPU, (obj), TYPE_CRIS_CPU)
-#define CRIS_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(CRISCPUClass, (obj), TYPE_CRIS_CPU)
+OBJECT_DECLARE_TYPE(CRISCPU, CRISCPUClass,
+                    cris_cpu, CRIS_CPU)
 
 /**
  * CRISCPUClass:
@@ -39,7 +36,7 @@
  *
  * A CRIS CPU model.
  */
-typedef struct CRISCPUClass {
+struct CRISCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
@@ -48,8 +45,7 @@ typedef struct CRISCPUClass {
     DeviceReset parent_reset;
 
     uint32_t vr;
-} CRISCPUClass;
+};
 
-typedef struct CRISCPU CRISCPU;
 
 #endif
diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
index b1f6045495..58158f374b 100644
--- a/target/hppa/cpu-qom.h
+++ b/target/hppa/cpu-qom.h
@@ -21,15 +21,12 @@
 #define QEMU_HPPA_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #define TYPE_HPPA_CPU "hppa-cpu"
 
-#define HPPA_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(HPPACPUClass, (klass), TYPE_HPPA_CPU)
-#define HPPA_CPU(obj) \
-    OBJECT_CHECK(HPPACPU, (obj), TYPE_HPPA_CPU)
-#define HPPA_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(HPPACPUClass, (obj), TYPE_HPPA_CPU)
+OBJECT_DECLARE_TYPE(HPPACPU, HPPACPUClass,
+                    hppa_cpu, HPPA_CPU)
 
 /**
  * HPPACPUClass:
@@ -38,15 +35,14 @@
  *
  * An HPPA CPU model.
  */
-typedef struct HPPACPUClass {
+struct HPPACPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} HPPACPUClass;
+};
 
-typedef struct HPPACPU HPPACPU;
 
 #endif
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index 3e96f8d668..0505472e86 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -22,6 +22,7 @@
 
 #include "hw/core/cpu.h"
 #include "qemu/notify.h"
+#include "qom/object.h"
 
 #ifdef TARGET_X86_64
 #define TYPE_X86_CPU "x86_64-cpu"
@@ -29,12 +30,8 @@
 #define TYPE_X86_CPU "i386-cpu"
 #endif
 
-#define X86_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(X86CPUClass, (klass), TYPE_X86_CPU)
-#define X86_CPU(obj) \
-    OBJECT_CHECK(X86CPU, (obj), TYPE_X86_CPU)
-#define X86_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(X86CPUClass, (obj), TYPE_X86_CPU)
+OBJECT_DECLARE_TYPE(X86CPU, X86CPUClass,
+                    x86_cpu, X86_CPU)
 
 typedef struct X86CPUModel X86CPUModel;
 
@@ -50,7 +47,7 @@ typedef struct X86CPUModel X86CPUModel;
  *
  * An x86 CPU model or family.
  */
-typedef struct X86CPUClass {
+struct X86CPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
@@ -72,8 +69,7 @@ typedef struct X86CPUClass {
     DeviceRealize parent_realize;
     DeviceUnrealize parent_unrealize;
     DeviceReset parent_reset;
-} X86CPUClass;
+};
 
-typedef struct X86CPU X86CPU;
 
 #endif
diff --git a/target/i386/sev.c b/target/i386/sev.c
index de4818da6d..d976634b8f 100644
--- a/target/i386/sev.c
+++ b/target/i386/sev.c
@@ -28,12 +28,13 @@
 #include "sysemu/runstate.h"
 #include "trace.h"
 #include "migration/blocker.h"
+#include "qom/object.h"
 
 #define TYPE_SEV_GUEST "sev-guest"
-#define SEV_GUEST(obj)                                          \
-    OBJECT_CHECK(SevGuestState, (obj), TYPE_SEV_GUEST)
-
 typedef struct SevGuestState SevGuestState;
+DECLARE_INSTANCE_CHECKER(SevGuestState, SEV_GUEST,
+                         TYPE_SEV_GUEST)
+
 
 /**
  * SevGuestState:
diff --git a/target/lm32/cpu-qom.h b/target/lm32/cpu-qom.h
index bdedb3759a..e9eb495bf0 100644
--- a/target/lm32/cpu-qom.h
+++ b/target/lm32/cpu-qom.h
@@ -21,15 +21,12 @@
 #define QEMU_LM32_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #define TYPE_LM32_CPU "lm32-cpu"
 
-#define LM32_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(LM32CPUClass, (klass), TYPE_LM32_CPU)
-#define LM32_CPU(obj) \
-    OBJECT_CHECK(LM32CPU, (obj), TYPE_LM32_CPU)
-#define LM32_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(LM32CPUClass, (obj), TYPE_LM32_CPU)
+OBJECT_DECLARE_TYPE(LM32CPU, LM32CPUClass,
+                    lm32_cpu, LM32_CPU)
 
 /**
  * LM32CPUClass:
@@ -38,15 +35,14 @@
  *
  * A LatticeMico32 CPU model.
  */
-typedef struct LM32CPUClass {
+struct LM32CPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} LM32CPUClass;
+};
 
-typedef struct LM32CPU LM32CPU;
 
 #endif
diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
index 88b11b60f1..a10429cf67 100644
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@@ -21,15 +21,12 @@
 #define QEMU_M68K_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #define TYPE_M68K_CPU "m68k-cpu"
 
-#define M68K_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(M68kCPUClass, (klass), TYPE_M68K_CPU)
-#define M68K_CPU(obj) \
-    OBJECT_CHECK(M68kCPU, (obj), TYPE_M68K_CPU)
-#define M68K_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(M68kCPUClass, (obj), TYPE_M68K_CPU)
+OBJECT_DECLARE_TYPE(M68kCPU, M68kCPUClass,
+                    m68k_cpu, M68K_CPU)
 
 /*
  * M68kCPUClass:
@@ -38,15 +35,14 @@
  *
  * A Motorola 68k CPU model.
  */
-typedef struct M68kCPUClass {
+struct M68kCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} M68kCPUClass;
+};
 
-typedef struct M68kCPU M68kCPU;
 
 #endif
diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
index 053ba44ee8..82734b9b2b 100644
--- a/target/microblaze/cpu-qom.h
+++ b/target/microblaze/cpu-qom.h
@@ -21,15 +21,12 @@
 #define QEMU_MICROBLAZE_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #define TYPE_MICROBLAZE_CPU "microblaze-cpu"
 
-#define MICROBLAZE_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(MicroBlazeCPUClass, (klass), TYPE_MICROBLAZE_CPU)
-#define MICROBLAZE_CPU(obj) \
-    OBJECT_CHECK(MicroBlazeCPU, (obj), TYPE_MICROBLAZE_CPU)
-#define MICROBLAZE_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(MicroBlazeCPUClass, (obj), TYPE_MICROBLAZE_CPU)
+OBJECT_DECLARE_TYPE(MicroBlazeCPU, MicroBlazeCPUClass,
+                    microblaze_cpu, MICROBLAZE_CPU)
 
 /**
  * MicroBlazeCPUClass:
@@ -38,15 +35,14 @@
  *
  * A MicroBlaze CPU model.
  */
-typedef struct MicroBlazeCPUClass {
+struct MicroBlazeCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} MicroBlazeCPUClass;
+};
 
-typedef struct MicroBlazeCPU MicroBlazeCPU;
 
 #endif
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 9d0df6c034..93fbbdca1b 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -21,6 +21,7 @@
 #define QEMU_MIPS_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #ifdef TARGET_MIPS64
 #define TYPE_MIPS_CPU "mips64-cpu"
@@ -28,12 +29,8 @@
 #define TYPE_MIPS_CPU "mips-cpu"
 #endif
 
-#define MIPS_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(MIPSCPUClass, (klass), TYPE_MIPS_CPU)
-#define MIPS_CPU(obj) \
-    OBJECT_CHECK(MIPSCPU, (obj), TYPE_MIPS_CPU)
-#define MIPS_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(MIPSCPUClass, (obj), TYPE_MIPS_CPU)
+OBJECT_DECLARE_TYPE(MIPSCPU, MIPSCPUClass,
+                    mips_cpu, MIPS_CPU)
 
 /**
  * MIPSCPUClass:
@@ -42,7 +39,7 @@
  *
  * A MIPS CPU model.
  */
-typedef struct MIPSCPUClass {
+struct MIPSCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
@@ -50,8 +47,7 @@ typedef struct MIPSCPUClass {
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
     const struct mips_def_t *cpu_def;
-} MIPSCPUClass;
+};
 
-typedef struct MIPSCPU MIPSCPU;
 
 #endif
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index 455553b794..d58761ccb1 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -21,6 +21,7 @@
 #define MOXIE_CPU_H
 
 #include "exec/cpu-defs.h"
+#include "qom/object.h"
 
 #define MOXIE_EX_DIV0        0
 #define MOXIE_EX_BAD         1
@@ -50,12 +51,8 @@ typedef struct CPUMoxieState {
 
 #define TYPE_MOXIE_CPU "moxie-cpu"
 
-#define MOXIE_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(MoxieCPUClass, (klass), TYPE_MOXIE_CPU)
-#define MOXIE_CPU(obj) \
-    OBJECT_CHECK(MoxieCPU, (obj), TYPE_MOXIE_CPU)
-#define MOXIE_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(MoxieCPUClass, (obj), TYPE_MOXIE_CPU)
+OBJECT_DECLARE_TYPE(MoxieCPU, MoxieCPUClass,
+                    moxie_cpu, MOXIE_CPU)
 
 /**
  * MoxieCPUClass:
@@ -63,14 +60,14 @@ typedef struct CPUMoxieState {
  *
  * A Moxie CPU model.
  */
-typedef struct MoxieCPUClass {
+struct MoxieCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} MoxieCPUClass;
+};
 
 /**
  * MoxieCPU:
@@ -78,14 +75,14 @@ typedef struct MoxieCPUClass {
  *
  * A Moxie CPU.
  */
-typedef struct MoxieCPU {
+struct MoxieCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
 
     CPUNegativeOffsetState neg;
     CPUMoxieState env;
-} MoxieCPU;
+};
 
 
 void moxie_cpu_do_interrupt(CPUState *cs);
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 4dddf9c3a1..1fa0fdaa35 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -23,6 +23,7 @@
 
 #include "exec/cpu-defs.h"
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 typedef struct CPUNios2State CPUNios2State;
 #if !defined(CONFIG_USER_ONLY)
@@ -31,12 +32,8 @@ typedef struct CPUNios2State CPUNios2State;
 
 #define TYPE_NIOS2_CPU "nios2-cpu"
 
-#define NIOS2_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(Nios2CPUClass, (klass), TYPE_NIOS2_CPU)
-#define NIOS2_CPU(obj) \
-    OBJECT_CHECK(Nios2CPU, (obj), TYPE_NIOS2_CPU)
-#define NIOS2_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(Nios2CPUClass, (obj), TYPE_NIOS2_CPU)
+OBJECT_DECLARE_TYPE(Nios2CPU, Nios2CPUClass,
+                    nios2_cpu, NIOS2_CPU)
 
 /**
  * Nios2CPUClass:
@@ -44,14 +41,14 @@ typedef struct CPUNios2State CPUNios2State;
  *
  * A Nios2 CPU model.
  */
-typedef struct Nios2CPUClass {
+struct Nios2CPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} Nios2CPUClass;
+};
 
 #define TARGET_HAS_ICE 1
 
@@ -174,7 +171,7 @@ struct CPUNios2State {
  *
  * A Nios2 CPU.
  */
-typedef struct Nios2CPU {
+struct Nios2CPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -191,7 +188,7 @@ typedef struct Nios2CPU {
     uint32_t reset_addr;
     uint32_t exception_addr;
     uint32_t fast_tlb_miss_addr;
-} Nios2CPU;
+};
 
 
 void nios2_tcg_init(void);
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index f37a52e153..d0a8ee657a 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -22,18 +22,15 @@
 
 #include "exec/cpu-defs.h"
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl.  */
 struct OpenRISCCPU;
 
 #define TYPE_OPENRISC_CPU "or1k-cpu"
 
-#define OPENRISC_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
-#define OPENRISC_CPU(obj) \
-    OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
-#define OPENRISC_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
+OBJECT_DECLARE_TYPE(OpenRISCCPU, OpenRISCCPUClass,
+                    openrisc_cpu, OPENRISC_CPU)
 
 /**
  * OpenRISCCPUClass:
@@ -42,14 +39,14 @@ struct OpenRISCCPU;
  *
  * A OpenRISC CPU model.
  */
-typedef struct OpenRISCCPUClass {
+struct OpenRISCCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} OpenRISCCPUClass;
+};
 
 #define TARGET_INSN_START_EXTRA_WORDS 1
 
@@ -305,14 +302,14 @@ typedef struct CPUOpenRISCState {
  *
  * A OpenRISC CPU.
  */
-typedef struct OpenRISCCPU {
+struct OpenRISCCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
 
     CPUNegativeOffsetState neg;
     CPUOpenRISCState env;
-} OpenRISCCPU;
+};
 
 
 void cpu_openrisc_list(void);
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 000c7d405b..5cf806a3a6 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -21,6 +21,7 @@
 #define QEMU_PPC_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #ifdef TARGET_PPC64
 #define TYPE_POWERPC_CPU "powerpc64-cpu"
@@ -28,14 +29,9 @@
 #define TYPE_POWERPC_CPU "powerpc-cpu"
 #endif
 
-#define POWERPC_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
-#define POWERPC_CPU(obj) \
-    OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU)
-#define POWERPC_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
+OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass,
+                    powerpc_cpu, POWERPC_CPU)
 
-typedef struct PowerPCCPU PowerPCCPU;
 typedef struct CPUPPCState CPUPPCState;
 typedef struct ppc_tb_t ppc_tb_t;
 typedef struct ppc_dcr_t ppc_dcr_t;
@@ -159,7 +155,7 @@ typedef struct PPCHash64Options PPCHash64Options;
  *
  * A PowerPC CPU model.
  */
-typedef struct PowerPCCPUClass {
+struct PowerPCCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
@@ -197,7 +193,7 @@ typedef struct PowerPCCPUClass {
     int  (*check_pow)(CPUPPCState *env);
     int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx);
     bool (*interrupts_big_endian)(PowerPCCPU *cpu);
-} PowerPCCPUClass;
+};
 
 #ifndef CONFIG_USER_ONLY
 typedef struct PPCTimebase {
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 3c4e1b3475..766e9c5c26 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -23,6 +23,7 @@
 #include "qemu/int128.h"
 #include "exec/cpu-defs.h"
 #include "cpu-qom.h"
+#include "qom/object.h"
 
 #define TCG_GUEST_DEFAULT_MO 0
 
@@ -1221,14 +1222,8 @@ struct PPCVirtualHypervisorClass {
 };
 
 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
-#define PPC_VIRTUAL_HYPERVISOR(obj)                 \
-    OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
-#define PPC_VIRTUAL_HYPERVISOR_CLASS(klass)         \
-    OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
-                       TYPE_PPC_VIRTUAL_HYPERVISOR)
-#define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
-                     TYPE_PPC_VIRTUAL_HYPERVISOR)
+DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
+                     PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
 #endif /* CONFIG_USER_ONLY */
 
 void ppc_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 383808bf88..ca75fc761e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -24,6 +24,7 @@
 #include "hw/registerfields.h"
 #include "exec/cpu-defs.h"
 #include "fpu/softfloat-types.h"
+#include "qom/object.h"
 
 #define TCG_GUEST_DEFAULT_MO 0
 
@@ -231,12 +232,8 @@ struct CPURISCVState {
     QEMUTimer *timer; /* Internal timer */
 };
 
-#define RISCV_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
-#define RISCV_CPU(obj) \
-    OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
-#define RISCV_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
+OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
+                    riscv_cpu, RISCV_CPU)
 
 /**
  * RISCVCPUClass:
@@ -245,13 +242,13 @@ struct CPURISCVState {
  *
  * A RISCV CPU model.
  */
-typedef struct RISCVCPUClass {
+struct RISCVCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} RISCVCPUClass;
+};
 
 /**
  * RISCVCPU:
@@ -259,7 +256,7 @@ typedef struct RISCVCPUClass {
  *
  * A RISCV CPU.
  */
-typedef struct RISCVCPU {
+struct RISCVCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
@@ -292,7 +289,7 @@ typedef struct RISCVCPU {
         bool mmu;
         bool pmp;
     } cfg;
-} RISCVCPU;
+};
 
 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 {
diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index 9054762326..6c5321078d 100644
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -20,18 +20,14 @@
 #define RX_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #define TYPE_RX_CPU "rx-cpu"
 
 #define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n")
 
-typedef struct RXCPU RXCPU;
-#define RX_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(RXCPUClass, (klass), TYPE_RX_CPU)
-#define RX_CPU(obj) \
-    OBJECT_CHECK(RXCPU, (obj), TYPE_RX_CPU)
-#define RX_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(RXCPUClass, (obj), TYPE_RX_CPU)
+OBJECT_DECLARE_TYPE(RXCPU, RXCPUClass,
+                    rx_cpu, RX_CPU)
 
 /*
  * RXCPUClass:
@@ -40,14 +36,14 @@ typedef struct RXCPU RXCPU;
  *
  * A RX CPU model.
  */
-typedef struct RXCPUClass {
+struct RXCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} RXCPUClass;
+};
 
 #define CPUArchState struct CPURXState
 
diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index 1630818c28..e2b2513711 100644
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -21,15 +21,12 @@
 #define QEMU_S390_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #define TYPE_S390_CPU "s390x-cpu"
 
-#define S390_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(S390CPUClass, (klass), TYPE_S390_CPU)
-#define S390_CPU(obj) \
-    OBJECT_CHECK(S390CPU, (obj), TYPE_S390_CPU)
-#define S390_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(S390CPUClass, (obj), TYPE_S390_CPU)
+OBJECT_DECLARE_TYPE(S390CPU, S390CPUClass,
+                    s390_cpu, S390_CPU)
 
 typedef struct S390CPUModel S390CPUModel;
 typedef struct S390CPUDef S390CPUDef;
@@ -50,7 +47,7 @@ typedef enum cpu_reset_type {
  *
  * An S/390 CPU model.
  */
-typedef struct S390CPUClass {
+struct S390CPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
@@ -64,9 +61,8 @@ typedef struct S390CPUClass {
     DeviceReset parent_reset;
     void (*load_normal)(CPUState *cpu);
     void (*reset)(CPUState *cpu, cpu_reset_type type);
-} S390CPUClass;
+};
 
-typedef struct S390CPU S390CPU;
 typedef struct CPUS390XState CPUS390XState;
 
 #endif
diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
index 72a63f3fd3..595814b8cb 100644
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@@ -21,6 +21,7 @@
 #define QEMU_SUPERH_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #define TYPE_SUPERH_CPU "superh-cpu"
 
@@ -28,12 +29,8 @@
 #define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r")
 #define TYPE_SH7785_CPU  SUPERH_CPU_TYPE_NAME("sh7785")
 
-#define SUPERH_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU)
-#define SUPERH_CPU(obj) \
-    OBJECT_CHECK(SuperHCPU, (obj), TYPE_SUPERH_CPU)
-#define SUPERH_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(SuperHCPUClass, (obj), TYPE_SUPERH_CPU)
+OBJECT_DECLARE_TYPE(SuperHCPU, SuperHCPUClass,
+                    superh_cpu, SUPERH_CPU)
 
 /**
  * SuperHCPUClass:
@@ -45,7 +42,7 @@
  *
  * A SuperH CPU model.
  */
-typedef struct SuperHCPUClass {
+struct SuperHCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
@@ -56,8 +53,7 @@ typedef struct SuperHCPUClass {
     uint32_t pvr;
     uint32_t prr;
     uint32_t cvr;
-} SuperHCPUClass;
+};
 
-typedef struct SuperHCPU SuperHCPU;
 
 #endif
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index 8b4d33c21e..5d7fb727bc 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -21,6 +21,7 @@
 #define QEMU_SPARC_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #ifdef TARGET_SPARC64
 #define TYPE_SPARC_CPU "sparc64-cpu"
@@ -28,12 +29,8 @@
 #define TYPE_SPARC_CPU "sparc-cpu"
 #endif
 
-#define SPARC_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(SPARCCPUClass, (klass), TYPE_SPARC_CPU)
-#define SPARC_CPU(obj) \
-    OBJECT_CHECK(SPARCCPU, (obj), TYPE_SPARC_CPU)
-#define SPARC_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(SPARCCPUClass, (obj), TYPE_SPARC_CPU)
+OBJECT_DECLARE_TYPE(SPARCCPU, SPARCCPUClass,
+                    sparc_cpu, SPARC_CPU)
 
 typedef struct sparc_def_t sparc_def_t;
 /**
@@ -43,7 +40,7 @@ typedef struct sparc_def_t sparc_def_t;
  *
  * A SPARC CPU model.
  */
-typedef struct SPARCCPUClass {
+struct SPARCCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
@@ -51,8 +48,7 @@ typedef struct SPARCCPUClass {
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
     sparc_def_t *cpu_def;
-} SPARCCPUClass;
+};
 
-typedef struct SPARCCPU SPARCCPU;
 
 #endif
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 193b6bbccb..d251ff80b8 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -21,6 +21,7 @@
 #define TILEGX_CPU_H
 
 #include "exec/cpu-defs.h"
+#include "qom/object.h"
 
 /* TILE-Gx common register alias */
 #define TILEGX_R_RE    0   /*  0 register, for function/syscall return value */
@@ -98,12 +99,8 @@ typedef struct CPUTLGState {
 
 #define TYPE_TILEGX_CPU "tilegx-cpu"
 
-#define TILEGX_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
-#define TILEGX_CPU(obj) \
-    OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU)
-#define TILEGX_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU)
+OBJECT_DECLARE_TYPE(TileGXCPU, TileGXCPUClass,
+                    tilegx_cpu, TILEGX_CPU)
 
 /**
  * TileGXCPUClass:
@@ -112,14 +109,14 @@ typedef struct CPUTLGState {
  *
  * A Tile-Gx CPU model.
  */
-typedef struct TileGXCPUClass {
+struct TileGXCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} TileGXCPUClass;
+};
 
 /**
  * TileGXCPU:
@@ -127,14 +124,14 @@ typedef struct TileGXCPUClass {
  *
  * A Tile-GX CPU.
  */
-typedef struct TileGXCPU {
+struct TileGXCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
 
     CPUNegativeOffsetState neg;
     CPUTLGState env;
-} TileGXCPU;
+};
 
 
 /* TILE-Gx memory attributes */
diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
index cd819e6f24..9e588c4c34 100644
--- a/target/tricore/cpu-qom.h
+++ b/target/tricore/cpu-qom.h
@@ -19,26 +19,22 @@
 #define QEMU_TRICORE_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 
 #define TYPE_TRICORE_CPU "tricore-cpu"
 
-#define TRICORE_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(TriCoreCPUClass, (klass), TYPE_TRICORE_CPU)
-#define TRICORE_CPU(obj) \
-    OBJECT_CHECK(TriCoreCPU, (obj), TYPE_TRICORE_CPU)
-#define TRICORE_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(TriCoreCPUClass, (obj), TYPE_TRICORE_CPU)
+OBJECT_DECLARE_TYPE(TriCoreCPU, TriCoreCPUClass,
+                    tricore_cpu, TRICORE_CPU)
 
-typedef struct TriCoreCPUClass {
+struct TriCoreCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-} TriCoreCPUClass;
+};
 
-typedef struct TriCoreCPU TriCoreCPU;
 
 #endif /* QEMU_TRICORE_CPU_QOM_H */
diff --git a/target/unicore32/cpu-qom.h b/target/unicore32/cpu-qom.h
index 7dd04515cb..c914273058 100644
--- a/target/unicore32/cpu-qom.h
+++ b/target/unicore32/cpu-qom.h
@@ -12,15 +12,12 @@
 #define QEMU_UC32_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #define TYPE_UNICORE32_CPU "unicore32-cpu"
 
-#define UNICORE32_CPU_CLASS(klass) \
-    OBJECT_CLASS_CHECK(UniCore32CPUClass, (klass), TYPE_UNICORE32_CPU)
-#define UNICORE32_CPU(obj) \
-    OBJECT_CHECK(UniCore32CPU, (obj), TYPE_UNICORE32_CPU)
-#define UNICORE32_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(UniCore32CPUClass, (obj), TYPE_UNICORE32_CPU)
+OBJECT_DECLARE_TYPE(UniCore32CPU, UniCore32CPUClass,
+                    unicore32_cpu, UNICORE32_CPU)
 
 /**
  * UniCore32CPUClass:
@@ -28,14 +25,13 @@
  *
  * A UniCore32 CPU model.
  */
-typedef struct UniCore32CPUClass {
+struct UniCore32CPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
 
     DeviceRealize parent_realize;
-} UniCore32CPUClass;
+};
 
-typedef struct UniCore32CPU UniCore32CPU;
 
 #endif
diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
index 3ea93ce1f9..299ce3e63c 100644
--- a/target/xtensa/cpu-qom.h
+++ b/target/xtensa/cpu-qom.h
@@ -30,15 +30,12 @@
 #define QEMU_XTENSA_CPU_QOM_H
 
 #include "hw/core/cpu.h"
+#include "qom/object.h"
 
 #define TYPE_XTENSA_CPU "xtensa-cpu"
 
-#define XTENSA_CPU_CLASS(class) \
-    OBJECT_CLASS_CHECK(XtensaCPUClass, (class), TYPE_XTENSA_CPU)
-#define XTENSA_CPU(obj) \
-    OBJECT_CHECK(XtensaCPU, (obj), TYPE_XTENSA_CPU)
-#define XTENSA_CPU_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(XtensaCPUClass, (obj), TYPE_XTENSA_CPU)
+OBJECT_DECLARE_TYPE(XtensaCPU, XtensaCPUClass,
+                    xtensa_cpu, XTENSA_CPU)
 
 typedef struct XtensaConfig XtensaConfig;
 
@@ -50,7 +47,7 @@ typedef struct XtensaConfig XtensaConfig;
  *
  * An Xtensa CPU model.
  */
-typedef struct XtensaCPUClass {
+struct XtensaCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
@@ -59,8 +56,7 @@ typedef struct XtensaCPUClass {
     DeviceReset parent_reset;
 
     const XtensaConfig *config;
-} XtensaCPUClass;
+};
 
-typedef struct XtensaCPU XtensaCPU;
 
 #endif