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| author | Leif Lindholm | 2021-01-08 19:51:50 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-01-12 11:09:13 +0100 |
| commit | f6450bcb6b2d3e4beae77141edce9e99cb8c277e (patch) | |
| tree | da6d47e4d8e31c9a6e0a8090ac909840eb09550f /target | |
| parent | target/arm: fix typo in cpu.h ID_AA64PFR1 field name (diff) | |
| download | qemu-f6450bcb6b2d3e4beae77141edce9e99cb8c277e.tar.gz qemu-f6450bcb6b2d3e4beae77141edce9e99cb8c277e.tar.xz qemu-f6450bcb6b2d3e4beae77141edce9e99cb8c277e.zip | |
target/arm: make ARMCPU.clidr 64-bit
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-3-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ed3e9fe2e4..fdbfcec2b0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -938,7 +938,7 @@ struct ARMCPU { uint32_t id_afr0; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint32_t clidr; + uint64_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ /* The elements of this array are the CCSIDR values for each cache, * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. |