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authorEdgar E. Iglesias2018-05-05 14:27:23 +0200
committerEdgar E. Iglesias2018-05-29 09:35:14 +0200
commitf7a66e3a8602b0498d340e5de959fbcf738a19b6 (patch)
tree236142b83a1a5ed447ee5766e64551bc964f278c /target
parenttarget-microblaze: Allow address sizes between 32 and 64 bits (diff)
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target-microblaze: Simplify address computation using tcg_gen_addi_i32()
Simplify address computation using tcg_gen_addi_i32(). tcg_gen_addi_i32() already optimizes the case when the immediate is zero. No functional change. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target')
-rw-r--r--target/microblaze/translate.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index bb6b5176c1..0d8ef77513 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -899,12 +899,7 @@ static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t)
/* Immediate. */
t32 = tcg_temp_new_i32();
if (!extimm) {
- if (dc->imm == 0) {
- tcg_gen_mov_i32(t32, cpu_R[dc->ra]);
- } else {
- tcg_gen_movi_i32(t32, (int32_t)((int16_t)dc->imm));
- tcg_gen_add_i32(t32, cpu_R[dc->ra], t32);
- }
+ tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm);
} else {
tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
}