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| author | Richard Henderson | 2018-12-18 03:01:47 +0100 |
|---|---|---|
| committer | Richard Henderson | 2019-01-28 16:03:34 +0100 |
| commit | 8afaf0506606f8003ef696df849c5a98637a7a83 (patch) | |
| tree | 89779034a934a38716364a0a8d04e8ab66c584c0 /tcg/README | |
| parent | tcg: Add write_aofs to GVecGen4 (diff) | |
| download | qemu-8afaf0506606f8003ef696df849c5a98637a7a83.tar.gz qemu-8afaf0506606f8003ef696df849c5a98637a7a83.tar.xz qemu-8afaf0506606f8003ef696df849c5a98637a7a83.zip | |
tcg: Add opcodes for vector saturated arithmetic
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/README')
| -rw-r--r-- | tcg/README | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tcg/README b/tcg/README index d22ee084b8..dd9fd9c86c 100644 --- a/tcg/README +++ b/tcg/README @@ -554,6 +554,15 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32. Similarly, v0 = -v1. +* ssadd_vec: +* sssub_vec: +* usadd_vec: +* ussub_vec: + + Signed and unsigned saturating addition and subtraction. If the true + result is not representable within the element type, the element is + set to the minimum or maximum value for the type. + * and_vec v0, v1, v2 * or_vec v0, v1, v2 * xor_vec v0, v1, v2 |