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| author | Pranith Kumar | 2016-07-14 22:20:13 +0200 |
|---|---|---|
| committer | Richard Henderson | 2016-09-16 17:12:11 +0200 |
| commit | f65e19bc2c9e8358e634d309606144ac2a3c2936 (patch) | |
| tree | 261b19dd382c67ff35f21ff53d64c58f03126764 /tcg/README | |
| parent | cpu-exec: Check -dfilter for -d cpu (diff) | |
| download | qemu-f65e19bc2c9e8358e634d309606144ac2a3c2936.tar.gz qemu-f65e19bc2c9e8358e634d309606144ac2a3c2936.tar.xz qemu-f65e19bc2c9e8358e634d309606144ac2a3c2936.zip | |
Introduce TCGOpcode for memory barrier
This commit introduces the TCGOpcode for memory barrier instruction.
This opcode takes an argument which is the type of memory barrier
which should be generated.
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Message-Id: <20160714202026.9727-2-bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/README')
| -rw-r--r-- | tcg/README | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tcg/README b/tcg/README index ce8bebab37..1d48aa963f 100644 --- a/tcg/README +++ b/tcg/README @@ -402,6 +402,23 @@ double-word product T0. The later is returned in two single-word outputs. Similar to mulu2, except the two inputs T1 and T2 are signed. +********* Memory Barrier support + +* mb <$arg> + +Generate a target memory barrier instruction to ensure memory ordering as being +enforced by a corresponding guest memory barrier instruction. The ordering +enforced by the backend may be stricter than the ordering required by the guest. +It cannot be weaker. This opcode takes a constant argument which is required to +generate the appropriate barrier instruction. The backend should take care to +emit the target barrier instruction only when necessary i.e., for SMP guests and +when MTTCG is enabled. + +The guest translators should generate this opcode for all guest instructions +which have ordering side effects. + +Please see docs/atomics.txt for more information on memory barriers. + ********* 64-bit guest on 32-bit host support The following opcodes are internal to TCG. Thus they are to be implemented by |