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| author | Richard Henderson | 2019-02-25 19:29:25 +0100 |
|---|---|---|
| committer | Richard Henderson | 2019-04-24 22:04:33 +0200 |
| commit | fce1296f135669eca85dc42154a2a352c818ad76 (patch) | |
| tree | 847ec48009722f8cc322e1661a080de798d77bc1 /tcg/README | |
| parent | tcg: Implement tcg_gen_extract2_{i32,i64} (diff) | |
| download | qemu-fce1296f135669eca85dc42154a2a352c818ad76.tar.gz qemu-fce1296f135669eca85dc42154a2a352c818ad76.tar.xz qemu-fce1296f135669eca85dc42154a2a352c818ad76.zip | |
tcg: Add INDEX_op_extract2_{i32,i64}
This will let backends implement the double-word shift operation.
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/README')
| -rw-r--r-- | tcg/README | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tcg/README b/tcg/README index 603f4df659..c30e5418a6 100644 --- a/tcg/README +++ b/tcg/README @@ -343,6 +343,13 @@ at bit 8. This operation would be equivalent to (using an arithmetic right shift). +* extract2_i32/i64 dest, t1, t2, pos + +For N = {32,64}, extract an N-bit quantity from the concatenation +of t2:t1, beginning at pos. The tcg_gen_extract2_{i32,i64} expander +accepts 0 <= pos <= N as inputs. The backend code generator will +not see either 0 or N as inputs for these opcodes. + * extrl_i64_i32 t0, t1 For 64-bit hosts only, extract the low 32-bits of input T1 and place it |