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| author | Richard Henderson | 2019-03-23 06:03:39 +0100 |
|---|---|---|
| committer | Richard Henderson | 2019-06-10 16:03:42 +0200 |
| commit | 269bd5d8f61c6b0825ed3c6a5fe01a3ad71c3b4a (patch) | |
| tree | b51b8c1ca4eadac1eee562a5e1671b778e022250 /tcg/i386 | |
| parent | cpu: Move icount_decr to CPUNegativeOffsetState (diff) | |
| download | qemu-269bd5d8f61c6b0825ed3c6a5fe01a3ad71c3b4a.tar.gz qemu-269bd5d8f61c6b0825ed3c6a5fe01a3ad71c3b4a.tar.xz qemu-269bd5d8f61c6b0825ed3c6a5fe01a3ad71c3b4a.zip | |
cpu: Move the softmmu tlb to CPUNegativeOffsetState
We have for some time had code within the tcg backends to
handle large positive offsets from env. This move makes
sure that need not happen. Indeed, we are able to assert
at build time that simple offsets suffice for all hosts.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/i386')
| -rw-r--r-- | tcg/i386/tcg-target.inc.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5f5b886c04..6ddeebf4bc 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1730,10 +1730,12 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_.f[mem_index].mask)); + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, mask)); tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_.f[mem_index].table)); + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, table)); /* If the required alignment is at least as large as the access, simply copy the address and mask. For lesser alignments, check that we don't |