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| author | WANG Xuerui | 2021-12-21 06:40:47 +0100 |
|---|---|---|
| committer | Richard Henderson | 2021-12-21 22:17:06 +0100 |
| commit | 7257809f62d8e01b6e54046b3893c80a8fbfa1b4 (patch) | |
| tree | a63ce4a32787a9c3fb7a5d8bd6dc6371eb1a24b6 /tcg/loongarch64/tcg-target.c.inc | |
| parent | tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops (diff) | |
| download | qemu-7257809f62d8e01b6e54046b3893c80a8fbfa1b4.tar.gz qemu-7257809f62d8e01b6e54046b3893c80a8fbfa1b4.tar.xz qemu-7257809f62d8e01b6e54046b3893c80a8fbfa1b4.zip | |
tcg/loongarch64: Implement deposit/extract ops
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-14-git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/loongarch64/tcg-target.c.inc')
| -rw-r--r-- | tcg/loongarch64/tcg-target.c.inc | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index d9508d5295..9eba8f8146 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -531,6 +531,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_extract_i32: + tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1); + break; + case INDEX_op_extract_i64: + tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1); + break; + + case INDEX_op_deposit_i32: + tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); + break; + case INDEX_op_deposit_i64: + tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -560,6 +574,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_ext_i32_i64: case INDEX_op_not_i32: case INDEX_op_not_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: return C_O1_I1(r, r); case INDEX_op_andc_i32: @@ -584,6 +600,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) /* LoongArch reg-imm bitops have their imms ZERO-extended */ return C_O1_I2(r, r, rU); + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + /* Must deposit into the same register as input */ + return C_O1_I2(r, 0, rZ); + default: g_assert_not_reached(); } |