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| author | Richard Henderson | 2020-12-12 17:38:21 +0100 |
|---|---|---|
| committer | Richard Henderson | 2021-01-07 16:09:41 +0100 |
| commit | 1da8de39a39c55560cb4bf0cea94d598fea035cd (patch) | |
| tree | 59d8b4160b3342019ef5fd8c1392af7812de0713 /tcg/mips/tcg-target.c.inc | |
| parent | tcg: Do not flush icache for interpreter (diff) | |
| download | qemu-1da8de39a39c55560cb4bf0cea94d598fea035cd.tar.gz qemu-1da8de39a39c55560cb4bf0cea94d598fea035cd.tar.xz qemu-1da8de39a39c55560cb4bf0cea94d598fea035cd.zip | |
util: Enhance flush_icache_range with separate data pointer
We are shortly going to have a split rw/rx jit buffer. Depending
on the host, we need to flush the dcache at the rw data pointer and
flush the icache at the rx code pointer.
For now, the two passed pointers are identical, so there is no
effective change in behaviour.
Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/mips/tcg-target.c.inc')
| -rw-r--r-- | tcg/mips/tcg-target.c.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 41be574e89..c255ecb444 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2660,7 +2660,7 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t addr) { qatomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); - flush_icache_range(jmp_addr, jmp_addr + 4); + flush_idcache_range(jmp_addr, jmp_addr, 4); } typedef struct { |