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| author | Richard Henderson | 2020-12-09 20:58:39 +0100 |
|---|---|---|
| committer | Richard Henderson | 2021-01-07 16:09:06 +0100 |
| commit | 07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1 (patch) | |
| tree | a22f2b213b2cb96c8e0e30c69bca9edb00b678bc /tcg/mips/tcg-target.h | |
| parent | tcg/i386: Adjust TCG_TARGET_HAS_MEMORY_BSWAP (diff) | |
| download | qemu-07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1.tar.gz qemu-07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1.tar.xz qemu-07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1.zip | |
tcg: Introduce INDEX_op_qemu_st8_i32
Enable this on i386 to restrict the set of input registers
for an 8-bit store, as required by the architecture. This
removes the last use of scratch registers for user-only mode.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/mips/tcg-target.h')
| -rw-r--r-- | tcg/mips/tcg-target.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 92c1d63da3..624248b81e 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -169,6 +169,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_clz_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_movcond_i64 use_movnz_instructions |