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| author | Pranith Kumar | 2017-06-30 17:39:46 +0200 |
|---|---|---|
| committer | Richard Henderson | 2017-07-10 09:10:23 +0200 |
| commit | 2ae96c157ab3155baf6595c08cf5d3fe3c023a60 (patch) | |
| tree | 07a47caef81fb50fea0e1d4cab1ecc1b8cd07fec /tcg/mips | |
| parent | tcg/aarch64: Enable indirect jump path using LDR (literal) (diff) | |
| download | qemu-2ae96c157ab3155baf6595c08cf5d3fe3c023a60.tar.gz qemu-2ae96c157ab3155baf6595c08cf5d3fe3c023a60.tar.xz qemu-2ae96c157ab3155baf6595c08cf5d3fe3c023a60.zip | |
util/cacheinfo: Fix warning generated by clang
Clang generates the following warning on aarch64 host:
CC util/cacheinfo.o
/home/pranith/qemu/util/cacheinfo.c:121:48: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths]
asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
^
/home/pranith/qemu/util/cacheinfo.c:121:28: note: use constraint modifier "w"
asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
^~
%w0
Constraint modifier 'w' is not (yet?) accepted by gcc. Fix this by increasing the ctr size.
Tested-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Message-Id: <20170630153946.11997-1-bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/mips')
0 files changed, 0 insertions, 0 deletions