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| author | Paolo Bonzini | 2015-05-05 09:18:22 +0200 |
|---|---|---|
| committer | Alexander Graf | 2015-06-03 23:56:56 +0200 |
| commit | 006f8638c62bca2b0caf609485f47fa5e14d8a3c (patch) | |
| tree | 45348a37b0929c631db152db3416901c5ddc7d39 /tcg/ppc/tcg-target.h | |
| parent | tci: do not use CPUArchState in tcg-target.h (diff) | |
| download | qemu-006f8638c62bca2b0caf609485f47fa5e14d8a3c.tar.gz qemu-006f8638c62bca2b0caf609485f47fa5e14d8a3c.tar.xz qemu-006f8638c62bca2b0caf609485f47fa5e14d8a3c.zip | |
tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS
This will be used to size the TLB when more than 8 MMU modes are
used by the target. Limitations come from the limited size of
the immediate fields (which sometimes, as in the case of Aarch64,
extend to instructions that shift the immediate).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <1424436345-37924-2-git-send-email-pbonzini@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'tcg/ppc/tcg-target.h')
| -rw-r--r-- | tcg/ppc/tcg-target.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 32ac4424db..7ce7048824 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -32,6 +32,7 @@ #define TCG_TARGET_NB_REGS 32 #define TCG_TARGET_INSN_UNIT_SIZE 4 +#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 typedef enum { TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, |