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authorRichard Henderson2020-10-17 05:09:02 +0200
committerRichard Henderson2021-02-02 23:12:31 +0100
commitc947deb13ea1a5c7b127177a3b5cc7d2f8607ab2 (patch)
treeb5cc445be50e60d0a08359eef7869797caeff27c /tcg/s390
parenttcg/riscv: Split out target constraints to tcg-target-con-str.h (diff)
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tcg/s390: Split out target constraints to tcg-target-con-str.h
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/s390')
-rw-r--r--tcg/s390/tcg-target-con-str.h28
-rw-r--r--tcg/s390/tcg-target.c.inc53
-rw-r--r--tcg/s390/tcg-target.h1
3 files changed, 42 insertions, 40 deletions
diff --git a/tcg/s390/tcg-target-con-str.h b/tcg/s390/tcg-target-con-str.h
new file mode 100644
index 0000000000..892d8f8c06
--- /dev/null
+++ b/tcg/s390/tcg-target-con-str.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define S390 target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
+/*
+ * A (single) even/odd pair for division.
+ * TODO: Add something to the register allocator to allow
+ * this kind of regno+1 pairing to be done more generally.
+ */
+REGS('a', 1u << TCG_REG_R2)
+REGS('b', 1u << TCG_REG_R3)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('A', TCG_CT_CONST_S33)
+CONST('I', TCG_CT_CONST_S16)
+CONST('J', TCG_CT_CONST_S32)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 8517e55232..3fec7fec5f 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -42,6 +42,19 @@
#define TCG_CT_CONST_S33 0x400
#define TCG_CT_CONST_ZERO 0x800
+#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16)
+/*
+ * For softmmu, we need to avoid conflicts with the first 3
+ * argument registers to perform the tlb lookup, and to call
+ * the helper function.
+ */
+#ifdef CONFIG_SOFTMMU
+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3)
+#else
+#define SOFTMMU_RESERVE_REGS 0
+#endif
+
+
/* Several places within the instruction set 0 means "no register"
rather than TCG_REG_R0. */
#define TCG_REG_NONE 0
@@ -403,46 +416,6 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
return false;
}
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'r': /* all registers */
- ct->regs = 0xffff;
- break;
- case 'L': /* qemu_ld/st constraint */
- ct->regs = 0xffff;
- tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
- tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
- break;
- case 'a': /* force R2 for division */
- ct->regs = 0;
- tcg_regset_set_reg(ct->regs, TCG_REG_R2);
- break;
- case 'b': /* force R3 for division */
- ct->regs = 0;
- tcg_regset_set_reg(ct->regs, TCG_REG_R3);
- break;
- case 'A':
- ct->ct |= TCG_CT_CONST_S33;
- break;
- case 'I':
- ct->ct |= TCG_CT_CONST_S16;
- break;
- case 'J':
- ct->ct |= TCG_CT_CONST_S32;
- break;
- case 'Z':
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
/* Test if a constant matches the constraint. */
static int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 641464eea4..c43d6aba84 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -159,5 +159,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
#endif