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| author | Richard Henderson | 2020-09-04 00:56:24 +0200 |
|---|---|---|
| committer | Richard Henderson | 2020-10-08 12:57:32 +0200 |
| commit | 74a117906b87ff9220e4baae5a7431d6f4eadd45 (patch) | |
| tree | d99fbe2a152523b0dd5b73fbd22e46aa2bdfd7cf /tcg/sparc/tcg-target.c.inc | |
| parent | tcg: Move sorted_args into TCGArgConstraint.sort_index (diff) | |
| download | qemu-74a117906b87ff9220e4baae5a7431d6f4eadd45.tar.gz qemu-74a117906b87ff9220e4baae5a7431d6f4eadd45.tar.xz qemu-74a117906b87ff9220e4baae5a7431d6f4eadd45.zip | |
tcg: Remove TCG_CT_REG
This wasn't actually used for anything, really. All variable
operands must accept registers, and which are indicated by the
set in TCGArgConstraint.regs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/sparc/tcg-target.c.inc')
| -rw-r--r-- | tcg/sparc/tcg-target.c.inc | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index e2de749af7..6775bd30fc 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -325,15 +325,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch (*ct_str++) { case 'r': - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; break; case 'R': - ct->ct |= TCG_CT_REG; ct->regs = ALL_64; break; case 'A': /* qemu_ld/st address constraint */ - ct->ct |= TCG_CT_REG; ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; reserve_helpers: tcg_regset_reset_reg(ct->regs, TCG_REG_O0); @@ -341,11 +338,9 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, tcg_regset_reset_reg(ct->regs, TCG_REG_O2); break; case 's': /* qemu_st data 32-bit constraint */ - ct->ct |= TCG_CT_REG; ct->regs = 0xffffffff; goto reserve_helpers; case 'S': /* qemu_st data 64-bit constraint */ - ct->ct |= TCG_CT_REG; ct->regs = ALL_64; goto reserve_helpers; case 'I': |