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author | Richard Henderson | 2021-01-29 02:07:41 +0100 |
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committer | Richard Henderson | 2021-02-05 21:24:14 +0100 |
commit | 2f74f45e32beb0ae24366128fdf685a5121c0f67 (patch) | |
tree | c42e7ad0532bfa98c43796ffb705d696ab44cae5 /tcg/tci/tcg-target-con-set.h | |
parent | tcg/tci: Fix TCG_REG_R4 misusage (diff) | |
download | qemu-2f74f45e32beb0ae24366128fdf685a5121c0f67.tar.gz qemu-2f74f45e32beb0ae24366128fdf685a5121c0f67.tar.xz qemu-2f74f45e32beb0ae24366128fdf685a5121c0f67.zip |
tcg/tci: Remove TCG_CONST
Restrict all operands to registers. All constants will be forced
into registers by the middle-end. Removing the difference in how
immediate integers were encoded will allow more code to be shared
between 32-bit and 64-bit operations.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci/tcg-target-con-set.h')
-rw-r--r-- | tcg/tci/tcg-target-con-set.h | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index 38e82f7535..f51b7bcb13 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -10,16 +10,12 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I2(r, r) -C_O0_I2(r, ri) C_O0_I3(r, r, r) -C_O0_I4(r, r, ri, ri) C_O0_I4(r, r, r, r) C_O1_I1(r, r) C_O1_I2(r, 0, r) -C_O1_I2(r, ri, ri) C_O1_I2(r, r, r) -C_O1_I2(r, r, ri) -C_O1_I4(r, r, r, ri, ri) +C_O1_I4(r, r, r, r, r) C_O2_I1(r, r, r) C_O2_I2(r, r, r, r) C_O2_I4(r, r, r, r, r, r) |