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| author | Paolo Bonzini | 2015-05-05 09:18:22 +0200 |
|---|---|---|
| committer | Alexander Graf | 2015-06-03 23:56:56 +0200 |
| commit | 006f8638c62bca2b0caf609485f47fa5e14d8a3c (patch) | |
| tree | 45348a37b0929c631db152db3416901c5ddc7d39 /tcg/tci/tcg-target.h | |
| parent | tci: do not use CPUArchState in tcg-target.h (diff) | |
| download | qemu-006f8638c62bca2b0caf609485f47fa5e14d8a3c.tar.gz qemu-006f8638c62bca2b0caf609485f47fa5e14d8a3c.tar.xz qemu-006f8638c62bca2b0caf609485f47fa5e14d8a3c.zip | |
tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS
This will be used to size the TLB when more than 8 MMU modes are
used by the target. Limitations come from the limited size of
the immediate fields (which sometimes, as in the case of Aarch64,
extend to instructions that shift the immediate).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <1424436345-37924-2-git-send-email-pbonzini@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'tcg/tci/tcg-target.h')
| -rw-r--r-- | tcg/tci/tcg-target.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 662d45c22f..cbf3f9b5a6 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -44,6 +44,7 @@ #define TCG_TARGET_INTERPRETER 1 #define TCG_TARGET_INSN_UNIT_SIZE 1 +#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 #if UINTPTR_MAX == UINT32_MAX # define TCG_TARGET_REG_BITS 32 |