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| author | Richard Henderson | 2021-01-29 01:55:57 +0100 |
|---|---|---|
| committer | Richard Henderson | 2021-02-05 21:24:14 +0100 |
| commit | 552672bae63dd2c470fc533f276b746bae90b813 (patch) | |
| tree | c20d9b1658b033f2689686c3ffe68d32ad7e0389 /tcg/tci | |
| parent | tcg/tci: Restrict TCG_TARGET_NB_REGS to 16 (diff) | |
| download | qemu-552672bae63dd2c470fc533f276b746bae90b813.tar.gz qemu-552672bae63dd2c470fc533f276b746bae90b813.tar.xz qemu-552672bae63dd2c470fc533f276b746bae90b813.zip | |
tcg/tci: Fix TCG_REG_R4 misusage
This was removed from tcg_target_reg_alloc_order and
tcg_target_call_iarg_regs on the assumption that it
was the stack. This was incorrectly copied from i386.
For tci, the stack is R15.
By adding R4 back to tcg_target_call_iarg_regs, adjust the other
entries so that 6 (or 12) entries are still present in the array,
and adjust the numbers in the interpreter.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci')
| -rw-r--r-- | tcg/tci/tcg-target.c.inc | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 7e3bed811e..aba7f75ad1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -181,9 +181,7 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, -#if 0 /* used for TCG_REG_CALL_STACK */ TCG_REG_R4, -#endif TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, @@ -206,19 +204,16 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, -#if 0 /* used for TCG_REG_CALL_STACK */ TCG_REG_R4, -#endif TCG_REG_R5, - TCG_REG_R6, #if TCG_TARGET_REG_BITS == 32 /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ + TCG_REG_R6, TCG_REG_R7, TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, - TCG_REG_R12, #endif }; |