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| author | Richard Henderson | 2021-02-01 10:23:07 +0100 |
|---|---|---|
| committer | Richard Henderson | 2021-06-19 17:51:11 +0200 |
| commit | bcb81061dc8173076d9669f969d132b998cd2af9 (patch) | |
| tree | b8ccf116e63ea6dade7803e6ba4b0325916d2b9d /tcg/tci | |
| parent | tcg/tci: Improve tcg_target_call_clobber_regs (diff) | |
| download | qemu-bcb81061dc8173076d9669f969d132b998cd2af9.tar.gz qemu-bcb81061dc8173076d9669f969d132b998cd2af9.tar.xz qemu-bcb81061dc8173076d9669f969d132b998cd2af9.zip | |
tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order
As the only call-clobbered regs for TCI, these should
receive the least priority.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci')
| -rw-r--r-- | tcg/tci/tcg-target.c.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8f3f9ef7d3..d54c01b9de 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -170,8 +170,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) } static const int tcg_target_reg_alloc_order[] = { - TCG_REG_R0, - TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, TCG_REG_R4, @@ -186,6 +184,8 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + TCG_REG_R1, + TCG_REG_R0, }; #if MAX_OPC_PARAM_IARGS != 6 |