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| author | Richard Henderson | 2014-03-27 02:56:31 +0100 |
|---|---|---|
| committer | Richard Henderson | 2014-06-23 16:31:56 +0200 |
| commit | b31284cecf36c75179dac828344fcce2b21204c4 (patch) | |
| tree | 6d6eaf18472aa7c9d340adff8706801642eadcfc /tcg | |
| parent | tcg-ppc64: Merge 32-bit ABIs into the prologue / frame code (diff) | |
| download | qemu-b31284cecf36c75179dac828344fcce2b21204c4.tar.gz qemu-b31284cecf36c75179dac828344fcce2b21204c4.tar.xz qemu-b31284cecf36c75179dac828344fcce2b21204c4.zip | |
tcg-ppc64: Fix sub2 implementation
All sorts of confusion on argument ordering.
Tested-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/ppc64/tcg-target.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 8d932eb47b..22cfa1e35b 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -2009,18 +2009,18 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_sub2_i64: a0 = args[0], a1 = args[1]; - if (a0 == args[5] || (!const_args[4] && a0 == args[4])) { + if (a0 == args[5] || (!const_args[3] && a0 == args[3])) { a0 = TCG_REG_R0; } if (const_args[2]) { - tcg_out32(s, SUBFIC | TAI(a0, args[3], args[2])); + tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); } else { - tcg_out32(s, SUBFC | TAB(a0, args[3], args[2])); + tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); } - if (const_args[4]) { - tcg_out32(s, (args[4] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); + if (const_args[3]) { + tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); } else { - tcg_out32(s, SUBFE | TAB(a1, args[5], args[4])); + tcg_out32(s, SUBFE | TAB(a1, args[5], args[3])); } if (a0 != args[0]) { tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); @@ -2146,7 +2146,7 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_deposit_i64, { "r", "0", "rZ" } }, { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } }, - { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } }, + { INDEX_op_sub2_i64, { "r", "r", "rI", "rZM", "r", "r" } }, { INDEX_op_mulsh_i64, { "r", "r", "r" } }, { INDEX_op_muluh_i64, { "r", "r", "r" } }, |