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| author | Cédric Le Goater | 2019-07-01 18:26:17 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-07-01 18:28:59 +0200 |
| commit | 6da4433fc5fa8aff1096cc651c8d313c70ee6f4d (patch) | |
| tree | 0ffaad3157d8abb9216a61ca5996a5d95ac38bd7 /tests/qapi-schema/comments.json | |
| parent | aspeed: add a RAM memory region container (diff) | |
| download | qemu-6da4433fc5fa8aff1096cc651c8d313c70ee6f4d.tar.gz qemu-6da4433fc5fa8aff1096cc651c8d313c70ee6f4d.tar.xz qemu-6da4433fc5fa8aff1096cc651c8d313c70ee6f4d.zip | |
aspeed/smc: add a 'sdram_base' property
The DRAM address of a DMA transaction depends on the DRAM base address
of the SoC. Inform the SMC controller model with this value.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190618165311.27066-15-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests/qapi-schema/comments.json')
0 files changed, 0 insertions, 0 deletions